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EDJ4216EFBG PDF даташит

Спецификация EDJ4216EFBG изготовлена ​​​​«Elpida Memory» и имеет функцию, называемую «256M words x 16 bits 4G bits DDR3L SDRAM».

Детали детали

Номер произв EDJ4216EFBG
Описание 256M words x 16 bits 4G bits DDR3L SDRAM
Производители Elpida Memory
логотип Elpida Memory логотип 

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EDJ4216EFBG Даташит, Описание, Даташиты
COVER
PRELIMINARY DATA SHEET
4G bits DDR3L SDRAM
EDJ4204EFBG (1024M words × 4 bits)
EDJ4208EFBG (512M words × 8 bits)
EDJ4216EFBG (256M words × 16 bits)
Specifications
• Density: 4G bits
• Organization
— 128M words × 4 bits × 8 banks (EDJ4204EFBG)
— 64M words × 8 bits × 8 banks (EDJ4208EFBG)
— 32M words × 16 bits × 8 banks (EDJ4216EFBG)
• Package
— 78-ball FBGA (EDJ4204EFBG, EDJ4208EFBG)
— 96-ball FBGA (EDJ4216EFBG)
— Lead-free (RoHS compliant) and Halogen-free
• Power supply: 1.35V (typ)
— VDD = 1.283V to 1.45V
— Backward compatible for VDD, VDDQ
= 1.5V ± 0.075V
• Data rate
— 1600Mbps/1333Mbps (max)
• 1KB page size
— Row address: A0 to A15
— Column address: A0 to A9, A11 (EDJ4204EFBG)
A0 to A9 (EDJ4208EFBG)
• 2KB page size (EDJ4216EFBG)
— Row address: A0 to A14
— Column address: A0 to A9
• Eight internal banks for concurrent operation
• Burst length (BL): 8 and 4 with Burst Chop (BC)
• Burst type (BT):
— Sequential (8, 4 with BC)
— Interleave (8, 4 with BC)
• /CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11
• /CAS Write Latency (CWL): 5, 6, 7, 8
• Precharge: auto precharge option for each burst
access
• Driver strength: RZQ/7, RZQ/6 (RZQ = 240)
• Refresh: auto-refresh, self-refresh
• Refresh cycles
— Average refresh period
7.8µs at 0°C TC +85°C
3.9µs at +85°C < TC +95°C
• Operating case temperature range
— TC = 0°C to +95°C
Features
• Double-data-rate architecture: two data transfers per
clock cycle
• The high-speed data transfer is realized by the 8 bits
prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS)
is transmitted/received with data for capturing data at
the receiver
• DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Posted /CAS by programmable additive latency for
better command and data bus efficiency
• On-Die Termination (ODT) for better signal quality
— Synchronous ODT
— Dynamic ODT
— Asynchronous ODT
• Multi Purpose Register (MPR) for pre-defined pattern
read out
• ZQ calibration for DQ drive and ODT
• Programmable Partial Array Self-Refresh (PASR)
• /RESET pin for Power-up sequence and reset function
• SRT range:
— Normal/extended
• Programmable Output driver impedance control
Document. No. E1922E11 (Ver. 1.1)
Date Published September 2012 (K) Japan
Printed in Japan
URL: http://www.elpida.com
©Elpida Memory, Inc. 2012









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EDJ4216EFBG Даташит, Описание, Даташиты
EDJ4204EFBG, EDJ4208EFBG, EDJ4216EFBG
Ordering Information
Part number
EDJ4204EFBG-GN-F
EDJ4204EFBG-DJ-F
EDJ4208EFBG-GN-F
EDJ4208EFBG-DJ-F
EDJ4216EFBG-GN-F
EDJ4216EFBG-DJ-F
Die
revision
F
Organization
(words × bits)
1024M × 4
F 512M × 8
F 256M × 16
Internal
banks
8
8
8
JEDEC speed bin
(CL-tRCD-tRP)
DDR3L-1600K (11-11-11)
DDR3L-1333H (9-9-9)
DDR3L-1600K (11-11-11)
DDR3L-1333H (9-9-9)
DDR3L-1600K (11-11-11)
DDR3L-1333H (9-9-9)
Package
78-ball FBGA
78-ball FBGA
96-ball FBGA
Note: 1. Please refer to the EDJ4204BFBG, EDJ4208BFBG, EDJ4216BFBG datasheet (E1923E) when using this device at 1.5V
operation, unless stated otherwise.
Part Number
E D J 42 04 E F BG - GN - F
Elpida Memory
Type
D: Packaged Device
Product Family
J: DDR3
Density / Bank
42: 4Gb / 8-bank
Organization
04: x4
08: x8
16: x16
Power Supply
E: 1.35V
Environment code
F: Lead Free (RoHS compliant)
and Halogen Free
Speed
GN: DDR3L-1600K (11-11-11)
DJ: DDR3L-1333H (9-9-9)
Package
BG: FBGA
Revision
Detailed Information
For detailed electrical specification and further information, please refer to the DDR3L SDRAM General Functionality
and Electrical Condition data sheet (E1927E).
Preliminary Data Sheet E1922E11 (Ver. 1.1)
2









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EDJ4216EFBG Даташит, Описание, Даташиты
EDJ4204EFBG, EDJ4208EFBG, EDJ4216EFBG
Pin Configurations
Pin Configurations (×4/×8 configuration)
/xxx indicates active low signal.
78-ball FBGA (×4 configuration)
1 23
A
VSS VDD NC
B
VSS VSSQ DQ0
C
VDDQ DQ2 DQS
D
VSSQ NC /DQS
E
VREFDQ VDDQ NC
F
NC VSS /RAS
G
ODT VDD /CAS
H
NC
/CS /WE
J
VSS BA0 BA2
K
VDD A3
A0
L
VSS A5
A2
M
VDD A7
A9
N
VSS /RESET A13
789
NC VSS VDD
DM VSSQ VDDQ
DQ1 DQ3 VSSQ
VDD VSS VSSQ
NC NC VDDQ
CK VSS NC
/CK VDD CKE
A10(AP) ZQ NC
A15 VREFCA VSS
A12(/BC) BA1 VDD
A1 A4 VSS
A11 A6 VDD
A14 A8 VSS
(Top view)
78-ball FBGA (×8 configuration)
1 23
A
VSS VDD NC
B
VSS VSSQ DQ0
C
VDDQ DQ2 DQS
D
VSSQ DQ6 /DQS
E
VREFDQ VDDQ DQ4
F
NC VSS /RAS
G
ODT VDD /CAS
H
NC
/CS /WE
J
VSS BA0 BA2
K
VDD A3
A0
L
VSS A5
A2
M
VDD A7
A9
N
VSS /RESET A13
789
NU/(/TDQS) VSS VDD
DM/TDQS VSSQ VDDQ
DQ1 DQ3 VSSQ
VDD VSS VSSQ
DQ7 DQ5 VDDQ
CK VSS NC
/CK VDD CKE
A10(AP) ZQ NC
A15 VREFCA VSS
A12(/BC) BA1 VDD
A1 A4 VSS
A11 A6 VDD
A14 A8 VSS
(Top view)
Pin name
Function
Pin name
Function
A0 to A15*3
Address inputs
A10(AP): Auto precharge
A12(/BC): Burst chop
/RESET*3
Active low asynchronous reset
BA0 to BA2*3
Bank select
VDD
Supply voltage for internal circuit
DQ0 to DQ7
Data input/output
VSS
Ground for internal circuit
DQS, /DQS
Differential data strobe
VDDQ
Supply voltage for DQ circuit
TDQS, /TDQS
Termination data strobe
VSSQ
Ground for DQ circuit
/CS*3
Chip select
VREFDQ
Reference voltage for DQ
/RAS, /CAS, /WE*3
Command input
VREFCA
Reference voltage for CA
CKE*3
Clock enable
ZQ
Reference pin for ZQ calibration
CK, /CK
Differential clock input
NC*1
No connection
DM
Write data mask
NU*2
Not usable
ODT*3
ODT control
Notes: 1.
2.
3.
Not internally connected with die.
Don't connect. Internally connected.
Input only pins (address, command, CKE, ODT and /RESET) do not supply termination.
Preliminary Data Sheet E1922E11 (Ver. 1.1)
3










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