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PDF AT84AS004 Data sheet ( Hoja de datos )
| Número de pieza | AT84AS004 | |
| Descripción | 10-bit 2 Gsps ADC | |
| Fabricantes | e2v | |
| Logotipo |  |
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AT84AS004
10-bit 2 Gsps ADC With1:4 DMUX
Datasheet
Features
• 10-bit Resolution
• 2 Gsps Sampling Rate
• Selectable 1:2 or 1:4 Demultiplexed Output
• 500 mVpp Differential 100Ω or Single-ended 50Ω Analog Input
• 100Ω Differential or Single-ended 50Ω Clock Input
• LVDS Output Compatibility
• Functions:
– ADC Gain Adjust
– Sampling Delay Adjust
– 1:4 Demultiplexed Simultaneous or Staggered Digital Outputs
– Data Ready Output with Asynchronous Reset
– Out-of-range Output Bit (11th Bit)
• Power Consumption: 6.5W
• Power Supplies: -5V, -2.2V, 3.3V and VPLUSD Output Power Supply
• Package
– Cavity Down EBGA 317 (Enhanced Ball Grid Array)
– 25 × 35 mm Dimensions
Performances
• 3 GHz Full Power Analog Input Bandwidth
• -0.5 dB Gain Flatness from DC up to 1.5 GHz
• Single-tone Performance at Fs = 2 Gsps, Full First and Second Nyquist (- 1 dBFS)
– ENOB = 7.8 Effective Bits, FIN = 1000 MHz
– SNR = 51 dBc, SFDR = -55 dBc, FIN = 1000 MHz
– ENOB = 7.5 Effective Bits, FIN = 2 GHz
– SNR = 50 dBc, SFDR = -54 dBc, FIN = 2 GHz
• Dual-tone Performance (IMD3) at Fs = 2 Gsps (-7 dBFS Each Tone)
– Fin1 = 945 MHz, Fin2 = 955 MHz: IMD3 = -60 dBFS
– Fin1 = 1545 MHz, Fin2 = 1555 MHz: IMD3 = -60 dBFS
Screening
• Temperature Range:
– Tamb > 0°C; TJ < 90°C (Commercial C Grade)
– Tamb > -40°C; TJ < 110°C (Industrial V Grade)
e2v semiconductors SAS 2007
Visit our website: www.e2v.com
for the latest version of the datasheet
0829E–BDC–10/07
1 page  
AT84AS004
4. Specifications
4.1 Absolute Maximum Ratings
Table 4-1. Absolute Maximum Ratings
Parameter
Symbol
Analog positive supply voltage
Digital positive supply voltage
Analog negative supply voltage
Digital positive supply voltage
Digital negative supply voltage
Maximum difference between
VPLUSD and VMINUSD
Analog input voltages
Maximum difference between
VIN and VINN
Clock input voltage
Maximum difference between
VCLK and VCLKN
Control input voltage
VCCA
VCCD
VEE
VPLUSD
VMINUSD
VPLUSD - VMINUSD
VIN or VINN
VIN or VINN
VCLK or VCLKN
VCLK - VCLKN
GA, SDA
Digital input voltage
SDAEN, B/GB, PGEB, DECB
ADC reset voltage
DRRB
DMUX function input voltage
RS, CLKTYPE, DRTYPE, SLEEP,
STAGG, BIST, DAEN
DMUX asynchronous reset
ASYNCRST
DMUX input voltage
DAI, DAIN
DMUX control voltage
CLKDACTRL, DACTRL
Maximum input voltage on DIODE
DIODE ADC
Maximum input current on DIODE
DIODE ADC
Junction temperature
TJ
Value
GND to 6
GND to 3.6
GND to -5.5
GND to 3
GND to -3
5
-1.5 to 1.5
-1.5 to 1.5
-1 to 1
-1 to 1
-1 to 0.8
-5 to 0.8
-0.3 to VCCA +0.3
-0.3 to VCCD +0.3
-0.3 to VCCD +0.3
-0.3 to VCCD +0.3
-0.3 to VCCD +0.3
700
1
135
Unit
V
V
V
V
V
V
V
V
Vpp
V
V
V
V
V
V
mV
mA
°C
Note:
1. Absolute maximum ratings are short term limiting values (referenced to GND = 0 V), to be applied individually, while other
parameters are within specified operating conditions. Long exposure to maximum ratings may affect device reliability.
2. All integrated circuits have to be handled with appropriate care to avoid damage due to ESD. Damage caused by inappropri-
ate handling or storage could range from performance degradation to complete failure.
e2v semiconductors SAS 2007
0829E–BDC–10/07
5
5 Page 
AT84AS004
Table 4-5. Transient and Switching Performances
Parameter
Test
Level
Symbol
Transient Performance
Bit error rate (1)
4 BER
ADC setting time (VIN-VINN = 400 mVpp)
Overvoltage recovery time
ADC step response rise/fall time (10 –90%)
Overshoot
Ringback
Switching Performance and Characteristics
Maximum clock frequency (2)
Minimum clock frequency (2)
Maximum clock pulse width (high)
Minimum clock pulse width (low)
Aperture delay (2)
Aperture uncertainty
DRRB pulse width
ASYNCRST pulse width
Output Data
Data Output Delay (3)
Data output delay Skew
Data pipeline delay
- Synchronized 1:2 ratio
- Synchronized 1:4 ratio
- Staggered 1:2 ratio
- Staggered 1:4 ratio
Data output rise/fall time (20% to 80%)
Output Clock
Output clock delay (3)
Output clock rise/fall time (20% –80%)
Output data to output clock propagation
delay
4
4
4
5
5
4
4
4
TS
ORT
FS Max
FS Min
TC1
TC2
TA
Jitter
TOD
Tskew
TPD
TR/TF
TDR
TR/TF
TD2-TD1
TOD-TDR
Min
10-11
2
0.22
0.22
1
1
Typ
400
80
4
2
150
160
150
7.1
5.5
7.5
4.5/5.5
4.5/5.5/6.5/7.5
6.6
200 500
Max
500
100
200
2.5
2.5
400
650
650
600
Unit
Error/
sample
ps
ps
ps
%
%
Gsps
Msps
ns
ns
ps
fs rms
ns
ns
ns
ps
Clock
cycles
ps
ns
ps
ps
e2v semiconductors SAS 2007
0829E–BDC–10/07
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AT84AS004.PDF ] | |
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