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Спецификация 3000 изготовлена «Intel» и имеет функцию, называемую «Memory Controller Hub». |
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Детали детали
Номер произв | 3000 |
Описание | Memory Controller Hub |
Производители | Intel |
логотип |
30 Pages
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Intel® 3000 and 3010 Chipset
Memory Controller Hub (MCH)
Datasheet
November 2008
Reference Number: 313953 Revision: 002
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED,
BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS
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AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING
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PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or
life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future
changes to them.
Intel® 3000 and 3010 chipsets may contain design defects or errors known as errata, which may cause the product to deviate
from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Intel, Pentium, Intel Celeron, Intel 6700PXH 64-bit PCI Hub, Intel I/O Controller Hub 7 (Intel ICH7), and the Intel logo are
trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright© 2006, Intel Corporation
2 Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
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Contents
1 Introduction............................................................................................................... 13
1.1 Terminology ..................................................................................................... 15
1.2 Reference Documents ........................................................................................ 16
1.3 MCH Overview .................................................................................................. 17
1.3.1 Host Interface........................................................................................ 17
1.3.2 System Memory Interface ....................................................................... 17
1.3.3 Direct Media Interface (DMI).................................................................... 18
1.3.4 PCI Express* Interface(s)........................................................................ 18
1.3.5 System Interrupts .................................................................................. 19
1.3.6 MCH Clocking ........................................................................................ 19
1.3.7 Power Management ................................................................................ 20
2 Signal Description....................................................................................................... 21
2.1 Host Interface Signals ........................................................................................ 23
2.2 DDR2 DRAM Channel A Interface ......................................................................... 25
2.3 DDR2 DRAM Channel B Interface ......................................................................... 26
2.4 DDR2 DRAM Reference and Compensation ............................................................ 27
2.5 PCI Express* Interface Signals ............................................................................ 27
2.6 Clocks, Reset, and Miscellaneous ......................................................................... 28
2.7 Direct Media Interface (DMI)............................................................................... 28
2.8 Power, Ground .................................................................................................. 29
2.9 Reset States and Pull-up/Pull-downs .................................................................... 29
3 MCH Register Description ............................................................................................ 33
3.1 Register Terminology ......................................................................................... 34
3.2 Platform Configuration ....................................................................................... 35
3.3 Configuration Mechanism ................................................................................... 37
3.3.1 Standard PCI Configuration Mechanism ..................................................... 37
3.3.2 PCI Express Enhanced Configuration Mechanism......................................... 38
3.4 Routing Configuration Accesses ........................................................................... 39
3.4.1 Internal Device Configuration Accesses ..................................................... 41
3.4.2 Bridge Related Configuration Accesses ...................................................... 41
3.5 I/O Mapped Registers ........................................................................................ 42
3.5.1 CONFIG_ADDRESS—Configuration Address Register ................................... 43
3.5.2 CONFIG_DATA—Configuration Data Register .............................................. 44
4 Host Bridge Registers (Device 0, Function 0) .................................................................. 45
4.1 Configuration Register Details (D0:F0) ................................................................. 47
4.1.1 VID—Vendor Identification (D0:F0)........................................................... 47
4.1.2 DID—Device Identification (D0:F0) ........................................................... 47
4.1.3 PCICMD—PCI Command (D0:F0) .............................................................. 48
4.1.4 PCISTS—PCI Status (D0:F0) .................................................................... 49
4.1.5 RID—Revision Identification (D0:F0) ......................................................... 50
4.1.6 CC—Class Code (D0:F0) .......................................................................... 50
4.1.7 MLT—Master Latency Timer (D0:F0) ......................................................... 50
4.1.8 HDR—Header Type (D0:F0) ..................................................................... 51
4.1.9 SVID—Subsystem Vendor Identification (D0:F0)......................................... 51
4.1.10 SID—Subsystem Identification (D0:F0) ..................................................... 51
4.1.11 CAPPTR—Capabilities Pointer (D0:F0) ....................................................... 52
4.1.12 EPBAR—Egress Port Base Address (D0:F0) ................................................ 52
4.1.13 MCHBAR—MCH Memory Mapped Register Range Base Address (D0:F0) ......... 53
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
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