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AS4C16M16D1 PDF даташит

Спецификация AS4C16M16D1 изготовлена ​​​​«Alliance Semiconductor» и имеет функцию, называемую «16M x 16 bit DDR Synchronous DRAM».

Детали детали

Номер произв AS4C16M16D1
Описание 16M x 16 bit DDR Synchronous DRAM
Производители Alliance Semiconductor
логотип Alliance Semiconductor логотип 

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AS4C16M16D1 Даташит, Описание, Даташиты
AS4C16M16D1
16M x 16 bit DDR Synchronous DRAM (SDRAM)
Alliance Memory Confidential
Advanced (Rev. 1.1, Sep. /2011)
Features
Fast clock rate: 200MHz
Differential Clock CK & CK
Bi-directional DQS
DLL enable/disable by EMRS
Fully synchronous operation
Internal pipeline architecture
Four internal banks, 4M x 16-bit for each bank
Programmable Mode and Extended Mode registers
- CAS Latency: 2, 2.5, 3
- Burst length: 2, 4, 8
- Burst Type: Sequential & Interleaved
Individual byte-write mask control
DM Write Latency = 0
Auto Refresh and Self Refresh
8192 refresh cycles / 64ms
Operating temperature range
- Commercial (0 ~ 70°C)
- Industrial (-40 ~ 85°C)
Precharge & active power down
Power supplies: VDD & VDDQ = 2.5V 0.2V
Interface: SSTL_2 I/O Interface
Package: 66 Pin TSOP II, 0.65mm pin pitch
- Pb free and Halogen free
Package: 60-Ball, 8x13x1.2 mm (max) TFBGA
- Pb free and Halogen Free
Overview
The AS4C16M16D1 SDRAM is a high-speed CMOS
double data rate synchronous DRAM containing 256 Mbits.
It is internally configured as a quad 4M x 16 DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal, CK). Data outputs occur
at both rising edges of CK and CK .d Read and write
accesses to the SDRAM are burst oriented; accesses start
at a selected location and continue for a programmed
number of locations in a programmed sequence. Accesses
begin with the registration of a BankActivate command
which is then followed by a Read or Write command. The
AS4C16M16D1 provides programmable Read or Write
burst lengths of 2, 4, or 8. An auto precharge function may
be enabled to provide a self-timed row precharge that is
initiated at the end of the burst sequence. The refresh
functions, either Auto or Self Refresh are easy to use. In
addition, AS4C16M16D1 features programmable DLL
option. By having a programmable mode register and
extended mode register, the system can choose the most
suitable modes to maximize its performance. These
devices are well suited for applications requiring high
memory band-width, result in a device particularly well
suited to high performance main memory and graphics
applications.
Table 1.Ordering Information
Part Number
Clock Data Rate Package Temperature Temp Range
AS4C16M16D1-5TCN 200MHz 400Mbps/pin 66pin TSOPII Commercial 0 ~ 70°C
AS4C16M16D1-5TIN 200MHz 400Mbps/pin 66pin TSOPII Industrial -40 ~ 85°C
AS4C16M16D1-5BCN 200MHz 400Mbps/pin 60ball TFBGA Commercial 0 ~ 70°C
AS4C16M16D1-5BIN 200MHz 400Mbps/pin 60ball TFBGA Industrial -40 ~ 85°C
T: indicates TSOP II package
B: indicates TFBGA package
C: indicates Commercial temp.
I: indicates Industrial temp.
N: indicates lead free ROHS
Alliance Memory, Inc.
551 Taylor Way, San Carlos, CA 94070
TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory, Inc. reserves the right to change products or specification without notice.









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AS4C16M16D1 Даташит, Описание, Даташиты
Figure 1. Pin Assignment (Top View)
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66 VSS
65 DQ15
64 VSSQ
63 DQ14
62 DQ13
61 VDDQ
60 DQ12
59 DQ11
58 VSSQ
57 DQ10
56 DQ9
55 VDDQ
54 DQ8
53 NC
52 VSSQ
51 UDQS
50 NC
49 VREF
48 VSS
47 UDM
46 CK
45 CK
44 CKE
43 NC
42 A12
41 A11
40 A9
39 A8
38 A7
37 A6
36 A5
35 A4
34 VSS
AS4C16M16D1
Figure 1.1 Ball Assignments (Top View)
123 789
A VSSQ DQ15 VSS
VDD
DQ0 VDDQ
B DQ14 VDDQ DQ13
DQ2 VSSQ DQ1
C DQ12 VSSQ DQ11
DQ4 VDDQ DQ3
D DQ10 VDDQ DQ9
DQ6 VSSQ DQ5
E DQ8 VSSQ UDQS
F VREF VSS UDM
G CK CK
H A12 CKE
LDQS VDDQ DQ7
LDM VDD
NC
WE CAS
RAS
CS
J A11 A9
K A8 A7
L A6 A5
BA1
A0
A2
BA0
A10
A1
M A4 VSS
VDD
A3
Alliance Memory, lnc. Confidential
2
Rev. 1.1
Sep. /2011









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AS4C16M16D1 Даташит, Описание, Даташиты
Figure 2. Block Diagram
CK
CK
CKE
DLL
CLOCK
BUFFER
CS
RAS
CAS
WE
COMMAND
DECODER
CONTROL
SIGNAL
GENERATOR
A10/AP
COLUMN
COUNTER
A0
A9
A11
A12
BA0
BA1
LDQS
UDQS
DQ0
DQ15
ADDRESS
BUFFER
REFRESH
COUNTER
DATA
STROBE
BUFFER
MODE
REGISTER
DQ
Buffer
LDM
UDM
AS4C16M16D1
4M x 16
CELL ARRAY
(BANK #0)
Column Decoder
4M x 16
CELL ARRAY
(BANK #1)
Column Decoder
4M x 16
CELL ARRAY
(BANK #2)
Column Decoder
4M x 16
CELL ARRAY
(BANK #3)
Column Decoder
Alliance Memory, lnc. Confidential
3
Rev. 1.1
Sep. /2011










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