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PDF M11B11664A Data sheet ( Hoja de datos )
| Número de pieza | M11B11664A | |
| Descripción | 64 K x 16 DRAM | |
| Fabricantes | EliteMT | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de M11B11664A (archivo pdf) en la parte inferior de esta página. Total 15 Páginas | ||
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(OLWH07
DRAM
FEATURES
y X16 organization
y EDO (Extended Data-Output) access mode
y 2 CAS Byte/Word Read/Write operation
y Single 5V ( ± 10%) power supply
y TTL-compatible inputs and outputs
y 256-cycle refresh in 4ms
y Refresh modes : RAS only, CAS BEFORE RAS (CBR)
and HIDDEN
y JEDEC standard pinout
y Key AC Parameter
tRAC
tCAC
tRC
tPC
-25 25 8 43 10
-30 30 9 55 12
-35 35 10 65 14
-40 40 11 75 16
M11B11664A
64 K x 16 DRAM
EDO PAGE MODE
ORDERING INFORMATION - PACKAGE
40-pin 400mil SOJ
44 / 40-pin 400mil TSOP (TypeII)
PRODUCT NO.
M11B11664A-25J
M11B11664A-30J
M11B11664A-35J
M11B11664A-40J
M11B11664A-25T
M11B11664A-30T
M11B11664A-35T
M11B11664A-40T
PACKING TYPE
SOJ
TSOPII
GENERAL DESCRIPTION
The M11B11664A is a randomly accessed solid state memory, organized as 65,536 x 16 bits device. It offers Extended
Data-Output , 5V( ± 10%) single power supply. Access time (-25,-30,-35,-40) and package type (SOJ, TSOP II) are optional
features of this family. All these family have CAS - before - RAS , RAS -only refresh and Hidden refresh capabilities.
Two access modes are supported by this device : Byte access and Word access. Use only one of the two CAS and leave
the other staying high will result in a BYTE access. WORD access happens when two CAS ( CASL , CASH ) are used. CASL
transiting low during READ or WRITE cycle will output or input data into the lower byte (IO0~IO7), and CASH transiting low will
output or input data into the upper byte (IO8~15).
PIN ASSIGNMENT
SOJ Top View
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 VSS
39 I/O15
38 I/O14
37 I/O13
36 I/O12
35 VSS
34 I/O11
33 I/O10
32 I/O9
31 I/O8
30 N C
29 CASL
28 CASH
27 OE
26 N C
25 A7
24 A6
23 A5
22 A4
21 VSS
TSOP (TypeII) Top View
VCC
I/O0
I/O1
I/O2
I/O3
VC C
I/O4
I/O5
I/O6
I/O7
NC
NC
WE
RAS
NC
A0
A1
A2
A3
VC C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 VSS
39 I/O15
38 I/O14
37 I/O13
36 I/O12
35 VSS
34 I/O11
33 I/O10
32 I/O9
31 I/O8
30 N C
29 CASL
28 CASH
27 OE
26 N C
25 A7
24 A6
23 A5
22 A4
21 VSS
Elite Memory Technology Inc
Publication Date : Dec. 2000
Revision : 1.3
1/15
1 page  
(OLWH07
M11B11664A
(Continued)
PARAMETER
-25 -30 -35 -40 UNIT Notes
SYMBOL
MIN MAX MIN MAX MIN MAX MIN MAX
Read Command Setup Time
Read Command Hold Time Reference to CAS
Read Command Hold Time Reference to RAS
CAS to Output in Low-Z
Output Buffer Turn-off Delay From CAS or RAS
Output Buffer Turn-off to OE
Write Command Setup Time
Write Command Hold Time
Write Command Hold Time(Reference to RAS )
Write Command Pulse Width
Write Command to RAS Lead Time
Write Command to CAS Lead Time
Data-in Setup Time
Data-in Hold Time
Data-in Hold Time (Reference to RAS )
RAS to WE Delay Time
Column Address to WE Delay Time
CAS to WE Delay Time
Transition Time (rise or fall)
Refresh Period (256 cycles)
RAS to CAS Precharge Time
CAS Setup Time(CBR REFRESH)
CAS Hold Time(CBR REFRESH)
OE Hold Time From WE During Read-Mode-
Write Cycle
OE Low to CAS High Setup Time
OE High Hold Time From CAS High
OE Precharge Time
OE Setup Prior to RAS During Hidden Refresh
Cycle
tRCS
tRCH
tRRH
tCLZ
tOFF1
tOFF2
tWCS
tWCH
tWCR
tWP
tRWL
tCWL
tDS
tDH
tDHR
tRWD
tAWD
tCWD
tT
tREF
tRPC
tCSR
tCHR
0000
0000
0000
3333
3 15 3 15 3 15 3 15
6888
0000
5555
22 26 30 34
5555
7 8 9 10
5678
0000
5555
22 26 30 34
34 46 51 56
21 31 34 36
17 25 26 27
1.5 50 1.5 50 2.5 50 2.5 50
4444
10 10 10 10
5 10 10 10
7 10 10 10
ns 15,18
ns 9,15,19
ns 9
ns 20
ns 10,17,20
ns 17,26
ns 11,15,18
ns 15,25
ns 15
ns 15
ns 15
ns 15,19
ns 12,20
ns 12,20
ns
ns 11
ns 11
ns 11,18
ns 2,3
ms
ns
ns 1,18
ns 1,19
tOEH
4
4
4
5
ns 16
tOES
4
4
4
5
ns
tOEHC
2
2
2
2
ns
tOEP
2
2
2
2
ns
tORD
0
0
0
0
ns
Last CAS Going Low to First CAS Returning
tCLCH
4
5
5
6
ns 21
High
Data Output Hold After CAS Returning Low
Output Disable Delay From WE
Read Setup Time Reference to RAS in CBR
Read Hold Time Reference to RAS in CBR
tCOH
tWHZ
tRSR
tRHR
3 3 3 3 ns
3 7 3 7 3 7 3 7 ns
5 5 5 5 ns
5 5 5 5 ns
Elite Memory Technology Inc
Publication Date : Dec. 2000
Revision : 1.3
5/15
5 Page 
(OLWH07
M11B11664A
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE
(Psuedo READ-MODIFY-WRITE)
VIH
RAS VIL
CAS
VIH
VIL
VIH
ADDR VIL
VIH
W E VIL
VI/OH
I/O VI/OL
VIH
OE VIL
tRASC
tCRP
t RC D
tCSH
tPC
tCAS
tCP
tCAS
tCP
tCP
tRSH
tCAS
tRAD
tASR tRAH
tAR
t ASC
tCAH
ROW
CO LU M N(A )
tRCS
tASC tCAH
COLUMN(B)
tRCH
tRAL
tASC tCAH
COLUMN(N)
t WCS
tWCH
tA A
tR AC
tCAC
OPEN
tOAC
tACP
tAA
tCAC
tCOH
tW HZ
VALID DATA(A)
VA L ID
DATA(B)
tDS tDH
VAL I D
DATA IN
tRP
tCP
ROW
VIH
RAS VIL
VIH
CASL,CASH VIL
VIH
ADDR VIL
VOH
I/O VOL
RAS ONLY REFRESH CYCLE
(ADDR = A0~A7 ; OE , WE = DON’T CARE)
tC RP
tASR
t RAH
ROW
tRAS
tRC
OPEN
tRP
tRP C
ROW
DON'T CARE
UNDEFINED
Elite Memory Technology Inc
Publication Date : Dec. 2000
Revision : 1.3
11/15
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet M11B11664A.PDF ] | |
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