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PDF ES5106 Data sheet ( Hoja de datos )
| Número de pieza | ES5106 | |
| Descripción | 3 1/2 DIGIT A/D CONVERTER W/LCD | |
| Fabricantes | Cyrustek | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ES5106 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
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ES5106
3 1/2 DIGIT A/D CONVERTER W/LCD
１．GENERAL DESCRIPTION
The ES 5106 is a low power monolithic CMOS 3 1/2 digit LCD
display A/D converter. The single chip ES 5106 provides all necessary
active devices which contains the internal clock, voltage reference, seven-
segment decoders, LCD display drivers and a back plane driver. The
improved internal zener reference voltage circuit gives the analog
common a small temperature coefficient of 60 ppm/℃ typically.
The high accuracy characteristics of the ES5106 perform very low
linearity error and rollover error. The high input impedance (>1012Ω) and
low input leakage current (1pA typical) give the ES5106 a good
application in the field of high impedance circuit measurement. The
differential input and reference are suitable for measuring bridge
transducer or ohms by using ratiometric method.
The dual slope conversion technique makes the ES5106 a good
normal and common mode rejection ratio. With a suitable oscillator
frequency, the ES5106 has a high rejection of 50HZ, 60HZ and 400HZ
line frequency noise.
With single power supply, a few passive components and a LCD
display, ES5106 can be built as a high performance panel meter. Existing
TSC7106 or ICL7106 based systems may be upgraded without changing
external, passive component values.
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1 page  
ES5106
3 1/2 DIGIT A/D CONVERTER W/LCD
PIN ASSIGNMENT
40-pin DIP package
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5 Page 
ES5106
3 1/2 DIGIT A/D CONVERTER W/LCD
System Timing
The oscillator frequency is divided by four prior to clocking the
internal decade counters. The signal integrate takes a fixed 1000
counts time period which is equal to 4000 clock pulses. The back
plane drive signal is derived by dividing clock frequency by 800. To
make a maximum rejection of line frequency (60Hz or 50Hz) noise
pickup, the signal integrate period should be a multiple of the line
frequency period. For 600Hz noise rejection, oscillator frequencies
of 120KHz, 80KHz, 60KHz, 48KHz, 40KHz, etc. should be selected.
For 50Hz rejection, oscillator frequencies of 100KHz, 50KHz,
40KHz, etc. would be suitable.
For all ranges of frequency Rosc should be 100KΩ, Cosc is
selected from the approximate equation f=0.45/RC. For 48KHz
clock (3readings/second), Cosc=100PF.
Integrating Resistor
The input buffer amplifier and integrator both have class A
output stage with 100μA of quiescent current and can supply
20μA drive currents with negligible linearity errors. The integrating
resistor should be chosen to remain in the output stage linear drive
region. It should be noticed that the integrating resistor should not
be so large such that the leakage currents of printed circuit board
will induce errors. For a 200mV full-scale the recommended
integrating resistor value is 47KΩ and for 2V full-scale is 470KΩ.
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11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet ES5106.PDF ] | |
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