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LX7730MFQ-EQ PDF даташит

Спецификация LX7730MFQ-EQ изготовлена ​​​​«Microsemi Corporation» и имеет функцию, называемую «64 Analog Input RAD Tolerant Telemetry Controller».

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Номер произв LX7730MFQ-EQ
Описание 64 Analog Input RAD Tolerant Telemetry Controller
Производители Microsemi Corporation
логотип Microsemi Corporation логотип 

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LX7730MFQ-EQ Даташит, Описание, Даташиты
Preliminary Datasheet
LX7730
64 Analog Input RAD Tolerant Telemetry
Controller
Description
The LX7730 is a spacecraft telemetry manager IC that
functions as a companion to the FPGA. The LX7730
contains a 64 universal input multiplexer that can be
configured as a mix of differential or single ended sensor
inputs. There is a programmable current source that can
be directed to any of the 64 universal inputs. The
universal inputs can be sampled with a 12 bit analog-to-
digital converter at a sample rate up to 25kHz. The
universal inputs can also function as variable bi-level
inputs with the threshold set by an internal 8 bit digital-to-
analog converter. There is an additional 10 bit digital-to-
analog current DAC with complementary outputs. Finally
there are 8 fixed threshold bi-level inputs.
The LX7730 is register programmable with 17
addressable eight bit registers. Two options are
available for communication with the host FPGA. First
there is an eight bit parallel bus with 5 address bits and a
read/write bit that can communicate at a speed of up to
25MHz. The second option is a pair of 50MBPS SPI
interfaces that can support redundant (alternating not
simultaneous) communication to two different hosts.
The LX7730 offers 1 kV ESD pin protection on all CH#
pins and 2kV on the other pins. The dielectric isolated
process is failsafe. The LX7730 has enable registers that
allow most of the device to be shut down to reduce power
consumption and supports cold sparing on its signal pins.
The controller is designed for use in rugged
environments. It is packaged in a 132 pin ceramic quad
flat pack and operates over a -55°C to 125°C
temperature range. It is radiation tolerant to 100krad TID
and 50krad ELDRs as well as Single event latch up.
Features
64 channel MUX
Break-before-make switching
25kSPS 12 bit ADC
2% Precision Adjustable Current Source
1% Precision 5.00V Source
Threshold Monitoring
8 x Bi-level Logic
10 bit DAC
Parallel or Dual SPI Interface
Radiation Tolerant: 100krad TID, 50kad ELDRS
Applications
Spacecraft Health Monitoring
Attitude Control
Payload Equipment
Main power
Internal LDOs
and Charge
Pump
VREF
Parallel
SPI_A
FPGA
SPI_B
Parallel
Interface
and
Registers
8 Current
Levels
12 Bit
ADC
64
Channel
Sensor
+ MUX
- Level Detect
8 Bit
DAC
10 Bit Current
DAC
+ 8 Bi-Level Inputs
- 2.5V
LX7730
Figure 1 · Product Highlight
LX7730 rev 0.9.2
©2015 Microsemi
1









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LX7730MFQ-EQ Даташит, Описание, Даташиты
64 Analog Input RAD Tolerant Telemetry Controller
Pin Configuration and Pinout
Programming & Test
Low Voltage
Power
HV Power
Pins
FPGA
Interface
Bi Level
Out to
FPGA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
VDD
CLK
/CE or /SSA
/OE or CLKA
/WE or MOSI_A
A0 or MISO_A
A1 or /SSB
A2 or CLKB
A3 or MOSI_B
A4 or MISO_B
+5V
GND
AGND
D0
D1
D2
D3
D4
D5
D6
D7
PTY
/ACK
RESET
BLO1
BLO2
BLO3
BLO4
BLO5
BLO6
BLO7
BLO8
AGND
AGND
CH45
CH44
CH43
CH42
CH41
CH40
CH39
CH38
CH37
CH36
CH35
CH34
CH33
CH32
CH31
CH30
CH29
CH28
CH27
CH26
CH25
CH24
CH23
CH22
CH21
CH20
CH19
CH18
CH17
CH16
CH15
AGND
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
Sensor
Inputs
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
References
DAC Bypass Bi Level Inputs
Figure 2 · Pinout
Ordering Information
Junction
Temperature
-55°C to 125°C
-55°C to 125°C
Commercial
Type
MIL-PRF-38535 Class V
MIL-PRF-38535 Class Q
Engineering Samples
Package
CQFP 132L
CQFP 132L
CQFP 132L
LX7730 rev 0.9.2
©2015 Microsemi
Part Number
LX7730MFQ-EV
LX7730MFQ-EQ
LX7730-ES
Packaging Type
Bulk / Tray
Bulk / Tray
Bulk
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LX7730MFQ-EQ Даташит, Описание, Даташиты
Pin Description
Pin Description
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12, 120, 132
13, 33, 41, 52,
67, 99
Pin Designator
Description
VDD
CLK
/CE or /SSA
/OE or CLKA
/WE or MOSI_A
A0 or MISO_A
A1 or/SSB
A2 or CLKB
A3 or MOSI_B
A4 or MISO_B
+5V
GND
VDD - Power reference pin This pin is used to reference the output logic
level to the FPGA. It connects to the FPGA I/O power supply.
System Clock Logic Input This clock input is used to time synchronous
logic needed to perform the ADC conversions. There is a weak pull-down on
this pin.
Chip enable or Slave Select channel A Logic Input Provides chip enable
for the parallel interface when /SPI_A and /SPI_B are high. Provides slave
select for the SPI channel A interface when the /SPI_A pin is pulled low. In
both cases the logic is active low. There is a weak pull-up on this pin.
Output enable or SPI Clock channel A Logic Input Provides output
enable (read enable) for the parallel interface when /SPI_A and /SPI_B are
high. Provides the clock for the SPI channel A interface when the /SPI_A pin
is pulled low. There is a weak pull-up on this pin.
Write enable or SPI MOSI channel A Logic Input Provides active low
write enable for the parallel interface when /SPI_A and /SPI_B are high.
Provides data input for the SPI channel A interface when the /SPI_A pin is
pulled low. There is a weak pull-up on this pin.
Address bit 0 or SPI MISO channel A Logic I/O Provides the address bit
0 (LSB) for the parallel interface when /SPI_A and /SPI_B are high.
Provides data output for the SPI channel A interface when the /SPI_A pin is
pulled low. There is a weak pull-down on this pin.
Address bit 1 or Slave Select channel A Logic Input Provides the
address bit 1 for the parallel interface when /SPI_A and /SPI_B are high.
Provides slave select for the SPI channel B interface when the /SPI_B pin is
pulled low. There is a weak pull-up on this pin.
Address bit 2 or SPI Clock channel B Logic Input Provides the address
bit 2 for the parallel interface when /SPI_A and /SPI_B are high. Provides
the clock for the SPI channel B interface when the /SPI_B pin is pulled low.
There is a weak pull-down on this pin.
Address bit 3 or SPI MOSI channel B Logic I/O Provides the address bit
3 for the parallel interface when /SPI_A and /SPI_B are high. Provides data
input for the SPI channel B interface when the /SPI_B pin is pulled low.
There is a weak pull-down on this pin.
Address bit 4 or SPI MISO channel A Logic I/O Provides the address bit
4 (MSB) for the parallel interface when /SPI_A and /SPI_B are high.
Provides data output for the SPI channel B interface when the /SPI_B pin is
pulled low. There is a weak pull-down on this pin.
+5V power rail Power Pin This pin is the low voltage power rail. It is
generated internally using a linear regulator connected to the VCC rail. A
bypass capacitor to GND is required.
Ground Power and Signal pin These pins provide a return path for power
supplies and a reference point for signals.
AGND
Analog Ground Signal pin These pin provides a reference point for
signals.
LX7730 rev 0.9.1
©2015 Microsemi
3










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Номер в каталогеОписаниеПроизводители
LX7730MFQ-EQ64 Analog Input RAD Tolerant Telemetry ControllerMicrosemi Corporation
Microsemi Corporation
LX7730MFQ-EV64 Analog Input RAD Tolerant Telemetry ControllerMicrosemi Corporation
Microsemi Corporation

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