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RTL8201N-GR PDF даташит

Спецификация RTL8201N-GR изготовлена ​​​​«REALTEK» и имеет функцию, называемую «SINGLE-CHIP/PORT 10/100M FAST ETHERNET PHYCEIVER».

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Номер произв RTL8201N-GR
Описание SINGLE-CHIP/PORT 10/100M FAST ETHERNET PHYCEIVER
Производители REALTEK
логотип REALTEK логотип 

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RTL8201N-GR Даташит, Описание, Даташиты
RTL8201N-GR
SINGLE-CHIP/PORT
10/100M FAST ETHERNET PHYCEIVER
WITH AUTO MDIX
DATASHEET
Rev. 1.1
22 August 2006
Track ID: JATR-1076-21
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com.tw









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RTL8201N-GR Даташит, Описание, Даташиты
RTL8201N
Datasheet
COPYRIGHT
©2006 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind, neither expressed nor implied,
including, but not limited to, the particular purpose. Realtek may make improvements and/or changes in
this document or in the product described in this document at any time. This document could include
technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the software engineer’s reference and provides detailed programming
information.
Though every effort has been made to ensure that this document is current and accurate, more information
may have become available subsequent to the production of this guide. In that event, please contact your
Realtek representative for additional information that may help in the development process.
REVISION HISTORY
Revision
1.0
1.1
Release Date
2006/06/29
2006/08/22
Summary
First release.
Revised pin names:
PWFBOUT18 => PWOUT18
PWFBOUT15 => PWOUT15.
Revised Pin Assignments:
DVDD33 (pin 18, 34, 49) => NC
DVDD15 (pin 32, 45, 59) => NC (see Table 7 and Table 8).
Revised Table 30, Power Dissipation, page 24.
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
With Auto MDIX
ii
Rev. 1.1









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RTL8201N-GR Даташит, Описание, Даташиты
RTL8201N
Datasheet
Table of Contents
1. GENERAL DESCRIPTION................................................................................................................................................1
2. FEATURES...........................................................................................................................................................................2
3. APPLICATIONS ..................................................................................................................................................................2
4. BLOCK DIAGRAM.............................................................................................................................................................3
5. PIN ASSIGNMENTS ...........................................................................................................................................................4
5.1. GREEN PACKAGE AND VERSION IDENTIFICATION .........................................................................................................4
6. PIN DESCRIPTIONS ..........................................................................................................................................................5
6.1. MII INTERFACE ............................................................................................................................................................5
6.2. SNI (SERIAL NETWORK INTERFACE) 10MBPS ONLY ....................................................................................................6
6.3. CLOCK INTERFACE .......................................................................................................................................................6
6.4. 10MBPS/100MBPS NETWORK INTERFACE....................................................................................................................7
6.5. DEVICE CONFIGURATION INTERFACE ...........................................................................................................................7
6.6. LED INTERFACE...........................................................................................................................................................8
6.7. POWER PINS .................................................................................................................................................................8
6.8. RESET AND OTHER PINS...............................................................................................................................................8
7. REGISTER DESCRIPTIONS ............................................................................................................................................9
7.1.
7.2.
7.3.
7.4.
7.5.
7.6.
7.7.
7.8.
7.9.
7.10.
7.11.
7.12.
REGISTER 0 BASIC MODE CONTROL REGISTER ............................................................................................................9
REGISTER 1 BASIC MODE STATUS REGISTER .............................................................................................................10
REGISTER 2 PHY IDENTIFIER REGISTER 1..................................................................................................................11
REGISTER 3 PHY IDENTIFIER REGISTER 2..................................................................................................................11
REGISTER 4 AUTO-NEGOTIATION ADVERTISEMENT REGISTER (ANAR) ....................................................................11
REGISTER 5 AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER (ANLPAR)......................................................12
REGISTER 6 AUTO-NEGOTIATION EXPANSION REGISTER (ANER) .............................................................................13
REGISTER 16 NWAY SETUP REGISTER (NSR).............................................................................................................13
REGISTER 17 LOOPBACK, BYPASS, RECEIVER ERROR MASK REGISTER (LBREMR) .................................................13
REGISTER 18 RX_ER COUNTER (REC) .....................................................................................................................14
REGISTER 19 SNR DISPLAY REGISTER.......................................................................................................................14
REGISTER 25 TEST REGISTER .....................................................................................................................................14
8. FUNCTIONAL DESCRIPTION.......................................................................................................................................15
8.1. MII AND MANAGEMENT INTERFACE ..........................................................................................................................15
8.1.1. Data Transition.....................................................................................................................................................15
8.1.2. Serial Management...............................................................................................................................................16
8.2. AUTO-NEGOTIATION AND PARALLEL DETECTION ......................................................................................................17
8.2.1. Setting the Medium Type and Interface Mode to MAC.........................................................................................17
8.2.2. UTP Mode and MII Interface ...............................................................................................................................18
8.2.3. UTP Mode and SNI Interface ...............................................................................................................................18
8.2.4. Fiber Mode and MII Interface..............................................................................................................................18
8.3. FLOW CONTROL SUPPORT ..........................................................................................................................................19
8.4. HARDWARE CONFIGURATION AND AUTO-NEGOTIATION ............................................................................................19
8.5. SERIAL NETWORK INTERFACE....................................................................................................................................20
8.6. POWER DOWN, LINK DOWN, POWER SAVING, AND ISOLATION MODES ......................................................................20
8.7. MEDIA INTERFACE .....................................................................................................................................................21
8.7.1. 100Base-TX Transmit & Receive Operation ........................................................................................................21
8.7.2. 100Base-FX Fiber Transmit & Receive Operation ..............................................................................................21
8.7.3. 10Base-T Transmit & Receive Operation .............................................................................................................22
8.8. REPEATER MODE OPERATION.....................................................................................................................................22
8.9. RESET, AND TRANSMIT BIAS ......................................................................................................................................22
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
With Auto MDIX
iii
Rev. 1.1










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