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PDF CDP1802ACD3 Data sheet ( Hoja de datos )
| Número de pieza | CDP1802ACD3 | |
| Descripción | High-Reliability CMOS 8-Bit Microprocessor | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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Data Sheet
CDP1802AC/3
October 17, 2008
FN1441.3
High-Reliability CMOS 8-Bit
Microprocessor
The CDP1802A/3 High-Reliability LSI CMOS 8-bit register
oriented Central-Processing Unit (CPU) is designed for use
as a general purpose computing or control element in a wide
range of stored-program systems or products.
The CDP1802A/3 includes all of the circuits required for
fetching, interpreting, and executing instructions which have
been stored in standard types of memories. Extensive
input/output (I/O) control features are also provided to
facilitate system design.
The 1800 Series Architecture is designed with emphasis on
the total microcomputer system as an integral entity so that
systems having maximum flexibility and minimum cost can be
realized. The 1800 Series CPU also provides a synchronous
interface to memories and external controllers for I/O devices,
and minimizes the cost of interface controllers. Further, the I/O
interface is capable of supporting devices operating in polled,
interrupt-driven, or direct memory-access modes.
The CDP1802AC/3 is functionally identical to its
predecessor, the CDP1802. The “A” version includes some
performance enhancements and can be used as a direct
replacement in systems using the CDP1802.
This type is supplied in a 40 Ld dual-in-line sidebrazed
ceramic package (D suffix).
Features
For Use In Aerospace, Military, and Critical Industrial
Equipment
• Minimum Instruction Fetch-Execute Time of 4.5µs
(Maximum Clock Frequency of 3.6MHz) at VDD = 5V,
TA = +25°C
• Operation Over the Full Military
Temperature Range . . . . . . . . . . . . . . . -55°C to +125°C
• Any Combination of Standard RAM and ROM Up to
65,536 Bytes
• 8-Bit Parallel Organization With Bi-directional Data
Bus and Multiplexed Address Bus
• 16x16 Matrix of Registers for Use as Multiple Program
Counters, Data Pointers, or Data Registers
• On-Chip DMA, Interrupt, and Flag Inputs
• High Noise Immunity . . . . . . . . . . . . . . . . . . 30% of VDD
• Pb-Free (RoHS compliant)
Ordering Information
PART
NUMBER
PART
MARKING
TEMP. RANGE
(°C)
CLOCK FREQUENCY
AT 5V
PACKAGE
PKG
DWG. #
CDP1802ACD3
CDP1802ACD3
-55 to +125
Up to 3.2MHz
40 Ld SBDIP
D40.6
NOTE: These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible
with both SnPb and Pb-free soldering operations.
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2002, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
CDP1802AC/3
Static Electrical Specifications All Limits are 100% Tested. Parameters with MIN and/or MAX limits are 100% tested at +25°C,
unless otherwise specified. Temperature limits established by characterization and are not
production tested. (Continued)
CONDITIONS
-55°C, +25°C
+125°C
PARAMETER
VOUT
(V)
VIN,
(V)
VCC, VDD
(V)
(Note 4)
MIN MAX MIN MAX UNITS
Output Voltage High-Level, VOH
Input Low Voltage, VIL
Input High Voltage, VIH
Input Leakage Current, IIN
-
0.5, 4.5
0.5, 4.5
Any
Input
0, 5
-
-
0, 5
5 4.9 - 4.8 - V
5 - 1.5 - 1.5 V
5 3.5 - 3.5 - V
5 - ±1 - ±5 µA
Three-State Output Leakage
Current, IOUT
0, 5 0, 5
5
- ±1 - ±5
NOTE:
4. 5V level characteristics apply to Part No. CDP1802AC/3, and 5V and 10V level characteristics apply to part No. CDP1802A/3.
µA
Timing Specifications
As a Function of T (T = 1/fCLOCK), CL = 50 pF. Parameters with MIN and/or MAX limits are 100% tested at
+25°C, unless otherwise specified. Temperature limits established by characterization and are not production
tested.
PARAMETER
VDD
(V)
LIMITS (Note 5)
-55°C, +25°C
+125°C
UNITS
High-Order Memory-Address Byte Setup to TPA
Time, tSU
High-Order Memory-Address Byte Hold After TPA Time, tH
Low-Order Memory-Address Byte Hold After WR Time, tH
CPU Data to Bus Hold After WR Time, tH
Required Memory Access Time Address to Data, tACC
NOTE:
5. These limits are not directly tested.
5
2T-450
2T-580
ns
5
T/2 +0
T/2 +0
ns
5
T-30
T-40
ns
5
T-170
T-250
ns
5
5T-300
5T-400
ns
Implicit Specifications
(Note 6) TA = -55°C to +25°C. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless
otherwise specified. Temperature limits established by characterization and are not production tested.
PARAMETER
SYMBOL
VDD
(V)
TYPICAL
VALUES
UNITS
Typical Total Power Dissipation
Idle “00” at M(0000), CL = 50pF
Effective Input Capacitance any Input
Effective Three-State Terminal Capacitance Data Bus
f = 2MHz
-
5
4 mW
- CIN -
5 pF
- - - 7.5 pF
Minimum Data Retention Voltage
- VDR - 2.4 V
Data Retention Current
-
IDR 2.4
10
µA
NOTE:
6. These specifications are not tested. Typical values are provided for guidance only.
5 FN1441.3
October 17, 2008
5 Page 
CDP1802AC/3
Machine Cycle Timing Waveforms (Propagation Delays Not Shown) (Continued)
01 234
CLOCK
56
70
12
34
56
70
TPA
TPB
MACHINE
CYCLE
INSTRUCTION
CYCLE n
FETCH (S0)
CYCLE (n + 1)
EXECUTE (S1)
MRD
N0 - N2
N=9-F
MWR
MEMORY
OUTPUT
DATA
BUS
(NOTE)
ALLOWABLE MEMORY ACCESS
MEMORY READ CYCLE
VALID OUTPUT
VALID DATA FROM INPUT DEVICE
MEMORY WRITE CYCLE
NOTE: USER GENERATED SIGNAL
“DON’T CARE” OR INTERNAL DELAYS
HIGH IMPEDANCE STATE
FIGURE 8. INPUT CYCLE TIMING WAVEFORMS
0 1 2 3 4 56 7 0 12 3 4 5 6 7 0
CLOCK
TPA
TPB
MACHINE
CYCLE
CYCLE n
CYCLE (n + 1)
INSTRUCTION
FETCH (S0)
EXECUTE (S1)
MRD
N0 - N2
N=1-9
ALLOWABLE MEMORY ACCESS
DATA BUS
DATA STROBE
(MRD ² TPB ² N)
(NOTE)
ALLOWABLE MEMORY ACCESS
VALID OUTPUT
VALID DATA FROM MEMORY
MEMORY READ CYCLE
MEMORY READ CYCLE
NOTE: USER GENERATED SIGNAL
“DON’T CARE” OR INTERNAL DELAYS
HIGH IMPEDANCE STATE
FIGURE 9. OUTPUT CYCLE TIMING WAVEFORMS
11 FN1441.3
October 17, 2008
11 Page | ||
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| PDF Descargar | [ Datasheet CDP1802ACD3.PDF ] | |
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