|
|
PDF AS8202B Data sheet ( Hoja de datos )
| Número de pieza | AS8202B | |
| Descripción | TTP-C2NF Communication Controller | |
| Fabricantes | ams | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AS8202B (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
|
No Preview Available !
AS8202B
TTP-C2NF Communication Controller
1 General Description
The AS8202B communication controller is an integrated device
supporting serial communication according to the TTP specification
version 1.1. It performs all communication tasks such as reception
and transmission of messages in a TTP cluster without interaction of
the host CPU. TTP provides mechanisms that allow the deployment
in high-dependability distributed real-time systems. It provides the
following services:
Predictable transmission of messages with minimal jitter
Fault-tolerant distributed clock synchronization
Consistent membership service with small delay
Masking of single faults
2 Key Features
Dual-channel controller for redundant data transfers
Dedicated controller supporting TTP (time-triggered protocol
class C standardized in SAE 6003)
Suited for dependable distributed real-time systems with
guaranteed response time
Asynchronous data rate up to 4 Mbit/s (MFM/Manchester)
Synchronous data rate 20 to 25 Mbit/s
Bus interface (speed, encoding) for each channel selectable
independently
Figure 1. Block Diagram
40 MHz oscillator clock support
16 MHz bus guardian clock with support for 16 MHz crystal or
16 MHz oscillator
Single power supply 3.3V, 0.35µm CMOS process
Full automotive temperature range (-40ºC to 125ºC)
16k x 16 SRAM for message, status, control area
(communication network interface) and for scheduling
information (MEDL)
4k x 16 (plus parity) instruction code RAM for protocol execution
code
Datasheet conforms to protocol revision 2.05
16k x 16 instruction code ROM containing startup execution
code and deprecated protocol code revision 1.00
16-bit non-multiplexed asynchronous host CPU interface
16-bit RISC architecture
Software tools, design support, development boards available
Visit www.tttech.com
Certification support package according to RTCA/DO-254 DAL
A available – Visit www.tttech.com
RoHS conform
3 Applications
The device is ideal for application fields such as, aerospace
according to DO-254 level A (e.g. flight control, power distribution,
engine control), industrial systems, and railway systems.
D[15:0]
A[11:0]
CEB
OEB
WEB
READYB
INTB
LED[2:0]
RAM_CLK_TESTSE
USE_RAM_CLK
AS8202B
XIN0
RESETB
Communication
Network
Interface
(CNI)
TTP Protocol
Processor Core
TTP Bus Unit
Asynchronous
Bus Interface
(MFM/
Manchester)
Synchronous
Bus Interface
(MII)
Bus
GuBaurdsi
Guaanrdian
Instruction Memory
RAM & ROM
Test Interface
RxD[1:0]
RxCLK[1:0]
RxDV[1:0]
RxER[1:0]
TxCLK[1:0]
TxD[1:0]
CTS[1:0]
XIN1
XOUT1
RAM_CLK_TESTSE
FTEST
STEST
FIDIS
TTEST
www.ams.com
Revision 1.0
1 - 20
1 page  
AS8202B
Datasheet - Pin Assignments
Table 1. Pin Descriptions
Pin Name
A[11:0]
D[15:0]
CEB
OEB
WEB
READYB
INTB
LED[2:0]
NC
Pin Number
48-42, 39-35
69-62, 58-51
76
77
78
79
28
33-31
1, 27, 40
Dir Description
TTL Input
Host Interface (CNI) Address Bus2
TTL input/output with tristate Host Interface (CNI) Data Bus, tristate
TTL Input with internal weak
pull-up
Host Interface (CNI) chip enable, active low
Host interface (CNI) output enable, active low
Host interface (CNI) write enable, active low
Host interface (CNI) transfer finish signal, active low, open
TTL output with internal weak drain3
pull-up at tristate
Host interface (CNI) time signal (interrupt), active low, open
drain
TTL output with internal weak
pull-down at tristate
Configurable generic output port
Not connected, leave open
1. This pin selects a clock multiplier of 1. This is the only supported operation mode.
2. The device is addressed at 16-bit data word boundaries. If the device is connected to a CPU with a byte-granular address bus, remem-
ber that A[11:0] of the AS8202B device has to be connected to A[12:1] of the CPU (considering a little endian CPU address bus)
3. At de-assertion READYB is driven to the inactive value (high) for a configurable time.
www.ams.com
Revision 1.0
5 - 20
5 Page 
AS8202B
Datasheet - Detailed Description
Table 5. Asynchronous DPRAM Interface
Symbol
Parameter
17
Read to Write Access Inactivity Time
(CEB, OEB low to CEB, WEB low)
18
Write to Write Access Inactivity Time
(CEB, WEB low to CEB, WEB low)
19
Write to Read Access Inactivity Time
(CEB, WEB low to CEB, OEB low)
Conditions
Min Typ Max Units
5
(see note 1)
ns
5
(see note 1,2)
ns
5
(see note 1,2)
ns
Notes:
1. Prior to starting a read or write access, CEB, WEB and OEB have to be stable for at least 5 ns (see symbol 3, 4, 8, 9). In addition the
designer has to consider the minimum inactivity time according to symbols 16, 17, 18, 19. For more information on the inactivity times
(see Figure 3).
2. To allow proper internal initialization, after finishing any write access (CEB or WEB is high) to the internal CONTROLLER_ON register,
CEB OEB and WEB have to be stable high within 200 ns (min = 8 Tc).
3. All values not tested during production, guaranteed by design.
Figure 3. Read/Write Access Inactivity Time
16 17 18 19
Read
Read
Write
Write
Read
CEB
OEB
WEB
www.ams.com
Revision 1.0
11 - 20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet AS8202B.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AS8202 | TTP/C-C2 Communication Controller |  austriamicrosystems AG |
| AS8202B | TTP-C2NF Communication Controller | ams |
| AS8202NF | TTP-C2NF Communication Controller | austriamicrosystems AG |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |