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PDF AS3953A Data sheet ( Hoja de datos )
| Número de pieza | AS3953A | |
| Descripción | 14443 High Speed Passive Tag Interface | |
| Fabricantes | ams | |
| Logotipo |  |
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AS3953A
14443 High Speed Passive Tag Interface
1 General Description
The AS3953A NFC interface IC (NFiC) delivers low cost, ultra low
power NFC forum functionality to multiple different applications. The
AS3953A is a analog front-end with integrated 14443A data framing
and SPI interface. It is designed to create a fast data link between an
ISO 14443A reader device (PCD) and a microcontroller. The
AS3953A is Passively powered meaning that it can be supplied from
the PCD magnetic field, eliminating the need of a continual external
supply. This makes the AS3953A perfect for wireless communication
to a low-power battery powered device.
The AS3953A is used with an appropriate antenna coil connected to
the terminals LC1 and LC2, and behaves as a normal passive ISO
144443A tag (PICC). After the anti-collision protocol is passed, the
PCD sends a Wake-up command, which wakes up the
microcontroller by sending an interrupt. From this point onwards, the
AS3953A serves as a data link between the microcontroller and the
PCD. AS3953A can also operate as NFCIP-1 target at 106 kb/s.
The AS3953A includes an onboard EEPROM that can be accessed
either from the PCD or from the microcontroller via the SPI interface.
This built-in flexibility makes it ideal for two types of applications:
Where personalization data is programmed by the PCD (even in
case the SPI side is not powered) and it is later read by
microcontroller through SPI interface.
Where log data is stored periodically by the microcontroller and
can then be read by the PCD even when the microcontroller is
not powered.
A regulated power supply voltage extracted from the PCD field is
also available on a pin and can be used as power supply for external
circuitry. For example, an external microcontroller and a sensor
could be powered from the PCD field combined with pass through
data rates up to 848Kbps, which means the AS3953A is ideal for
contactless passive programming of MCU systems. The AS3953A
can also operate as a stand-alone ISO 14443A tag.
The AS3953A supports ISO 14443A up to Level-4, meaning a
contactless smart card or an NFC forum compatible tag (Tag Type 4)
can be built. Having a NFC Forum compatible tag interface allows
the AS3953A to be used in an application where a standard NFC
enabled phone is used as a PCD.
2 Key Features
ISO 14443A compliant to Level-4
NFCIP-1 target at 106 kb/s
1k bit EEPROM (108 bytes of user memory)
Configurable wake-up interrupt (after tag is selected or using
proprietary command)
Powered from external magnetic field with the possibility to
draw up to 5mA
7 byte UID
User configurable regulated voltage extracted from external
magnetic field
Bit rates from 106 Kbps till 848 Kbps
Integrated resonant capacitor
Integrated buffer capacitor
4-wire Serial Peripheral Interface (SPI) with 32 byte FIFO
Wide SPI power supply range (1.65V to 3.6V)
Wide temperature range: -40ºC to 85ºC
Available as WLCSP 10-bumps (10-pin MLPD (3x3mm) and
Gold bumped dies)
3 Applications
The device is ideal for applications like Passive wake-up,
Multipurpose HF interface to a controller, Low power or passive
programming, Ultra Low Power Data Logger, RFID Programmable
configuration EEPROM, ISO 14443A smart card, NFC Forum Tag
Type 4, and Bluetooth and Wi-Fi pairing.
Figure 1. AS3953A Block Diagram
VP_REG
VP_INT
Power
Manager
VDD
AS3953A
VP_SPI
LC1
AFE
LC2
IRQ
POR
Logic
EEPROM
Level
Shifters
SPI
VSS
www.ams.com
Revision 1.3
1 - 42
1 page  
AS3953A
Datasheet - Pin Assignments
4.1 Pin Descriptions
Table 1. Pin Descriptions
MLPD
-
1
2
3
4
5
6
7
8
9
10
11
Pin Number
WL-CSP
Gold Bumped
Die
-0
C4 1
B4 2
B3 3
B2 4
C1 5
A1 6
B1 7
A2 8
A3 9
A4 10
--
Pin Name
TEST
VP_SPI
VP_REG
LC1
LC2
VSS
/SS
SCLK
MOSI
MISO
IRQ
Exposed Pad
Pin Type
Description
Internal use
Supply pad
Analog output
No connection
Positive supply of SPI interface
Regulator output
Analog I/O
Connection to tag coil
Supply pad
Digital input
Digital output / tristate
Digital output
Supply
Ground, die substrate potential
Serial Peripheral Interface enable (active low)
Serial Peripheral Interface clock
Serial Peripheral Interface data input
Serial Peripheral Interface data output
Interrupt request output (active high)
Exposed pad to be connected to ground (optional)
www.ams.com
Revision 1.3
5 - 42
5 Page 
AS3953A
Datasheet - Detailed Description
7.3 Power Manager
Power manager is controlling the positive supply voltage of the PICC Logic, EEPROM and SPI Interface (VDD). Its inputs are VP_INT (rectified
and regulated supply extracted from PCD field) and the VP_SPI (SPI power supply from external).
In standby mode, when the AS3953A is not in a PCD field (condition is that rectified supply voltage is below HF_PON threshold) and the SPI is
not active (/SS is high) the VDD supply is disconnected not to consume on VP_SPI. The only consumption on VP_SPI is leakage of level shifters
and SPI pins.
When the AS3953A is placed in a PCD field the VDD is connected to VP_INT. This happens once the VP_INT level is above the HF_PON
threshold.
VP_SPI is connected to VDD only when the AS3953A is not in the PCD field (rectified supply voltage is below HF_PON threshold) and the SPI
interface is activated by pulling /SS signal low. The switch to VP_SPI is controlled by /SS signal. The deactivation is delayed by 0.7ms min., thus
the switch stays on in case the time between successive SPI activations is short. During EEPROM writing, which is activated over the SPI, the
switch is also active.
At activation of the switch the time between the falling edge of /SS signal and rising edge of SCLK has to be at least 50µs to allow charging of
internal VDD buffer capacitor and expiration of POR signal. Please note that the only SPI operations, which are allowed in this mode, are reading
and writing of the EEPROM and registers.
Figure 5. Power Manager Concept
PON
/SS
EEPROM
WRITE
VP_INT
DELAY
VP_SPI
VDD
7.4 ISO 14443A Framing Mode
When Framing mode is selected the PICC logic performs receive and transmit framing according to the selected ISO 14443A bit rate.
During reception it recognizes the SOF, EOF and data bits, performs parity and CRC check, organizes the received data in bytes and places
them in the FIFO.
During transmit, it operates inversely, it takes bytes from FIFO, generates parity and CRC bits, adds SOF and EOF and performs data encoding.
Default bit rate in the Framing mode is fc/128 (~106 kb/s). Higher data rates may be configured by controller by writing the Bit Rate Definition
Register.
In order to respect the PCD-to-PICC frame delay according to ISO14443-3 at data rate fc/128 bit the PICC logic synchronizes the response to
the beginning of the next response window, but not earlier than window with n=9.
In this mode the EEPROM can be accessed via SPI when the RF field is active.
www.ams.com
Revision 1.3
11 - 42
11 Page | ||
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| PDF Descargar | [ Datasheet AS3953A.PDF ] | |
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