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PDF AS3524 Data sheet ( Hoja de datos )
| Número de pieza | AS3524 | |
| Descripción | Advanced Audio Processor System | |
| Fabricantes | austriamicrosystems AG | |
| Logotipo |  |
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AS3524 C21 / C22
Data Sheet, Confidential
austriamicrosystems
AS3524
Advanced Audio Processor System
å
1 Description
The AS3524 implements a highly flexible and fully integrated digital
audio processor system combining strong calculating power and
high performance interfaces commonly used within audio player
systems.
Using advanced 0.13µm process technology and large on chip
RAM leads to outstanding low power consumption of 0.3 mW/MHz
for the ARM922T microcontroller core and 0.6 mW/MHz for the
overall system measured with a typical MP3 player SW application.
Based on a powerful ARM9TDMI capable of performing up to
200MIPS it is suited to run MP3, AAC, WMA, OGG… decoders and
encoders and, in addition, it can perform extensive user interfaces,
motion graphics support, video playback and much more.
The AS3524 SOC (system-on-a-Chip) features dedicated high
speed interfaces for ATA IDE, USB2.0 HS-OTG and SDRAM
ensuring maximum performance for download, upload, and
playback.
Furthermore interfaces for NAND flashes, MMC/SD cards and
Memory Stick ensure most flexible system design possibilities.
Hardware support for parallel interfaces lower the CPU load serving
complex and/or colour user interfaces.
Additional serial high-speed data and control interfaces guarantee
the connection to other peripherals and or processors in the system.
Two independently programmable PLLs generate the required
frequencies for audio playback/recording, for the processor core
and for the USB interface at the same time.
Datasheet, Confidential
Key Features
1.1 Digital Core
Embedded 32-Bit RISC Controller
• ARM922TDMI RISC CPU
• 2.5Mbit on-chip RAM
• 1Mbit on chip ROM
• Clock speed max. 250MHz (200MIPS)
• Standard JTAG interface
USB 2.0 HS & OTG Interface
• Up to 480Mbit/s transfer speed
• USB 2.0 HS/FS physical inlcuding OTG support
• USB 2.0 HS/FS digital core including OTG host
• Dedicated dual port buffer RAM
• DMA bus master functionality
IDE Host Controller
• Supporting Ultra ATA 33/66/100/133 modes
• Programmable IO and Multi-word DMA capability
• Dedicated dual port buffer RAM
• DMA bus master functionality
External Memory Controller
• Dynamic memory interface
• Asynchronous static memory
• DMA bus master functionality
DMA Controller
• Single Master DMA controller
• 2 DMA channels possible at the same time
• 16 DMA requests supported
Interrupt Controller
• Support for 32 standard interrupts
• Support for 16 vectored IRQ interrupts
Audio Subsystem Interface
• Dedicated 2 wire serial control master
• I2S input and output with dual port buffer RAM
Nand Flash Interface
• 8 and 16bit flash support
• 3, 4 & 5 byte address support
• hardware ECC
© 2003-2010, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1.12
1 - 124
1 page  
AS3524 C21 / C22
Data Sheet, Confidential
austriamicrosystems
5.3.11
5.3.12
5.3.13
5.3.14
5.3.15
NAND Flash Interface ........................................................................................................................ 63
DBOP - Data Block Output Port ......................................................................................................... 74
UART – Universal Asynchronous Receiver/Transmitter.................................................................... 84
CGU - Clock generation unit .............................................................................................................. 91
CCU - Chip Control Unit .................................................................................................................. 105
6 PINOUT AND PACKAGING ...............................................................................110
6.1 Package Variants.......................................................................................................................................... 110
6.2 CTBGA180 Package Drawings ................................................................................................................... 110
6.2.1
Marking............................................................................................................................................. 110
6.2.2
CTBGA180 Package Ball-out ........................................................................................................... 111
6.2.3
CTBGA180 Ball List ........................................................................................................................ 111
6.3 Pad Cell Description..................................................................................................................................... 119
6.3.1
Digital Pads ....................................................................................................................................... 119
7 APPENDIX ..........................................................................................................120
7.1 Memory MAP ............................................................................................................................................... 120
7.2 Register definitions....................................................................................................................................... 122
7.2.1
Base Address definitions................................................................................................................... 122
8 ORDERING INFORMATION ...............................................................................123
9 COPYRIGHT .......................................................................................................124
10 DISCLAIMER ......................................................................................................124
11 CONTACT INFORMATION.................................................................................124
© 2003-2010, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1.12
5 - 124
5 Page 
AS3524 C21 / C22
Data Sheet, Confidential
austriamicrosystems
4.2.4 Start-up Sequence for Supply Voltages
To ensure correct start-up special timing constraints are given for circuit power-on. Also to ensure correct functionality of the USB Bootloader
certain restrictions must be met.
For start-up it has to be guaranteed that VDD_CORE is not applied before all other peripheral supply voltages are switched on. The only
exception are the USB suppies (USB_VDDA33C, USB_VDDA33T), which can be switched on and off independently of all other supplies.
Figure 2: AS3524 startup
VDD_PERI_L
=VDD_PERI_R
T1
T2
T3
T4
VDD_MEM
USB_VDDA33C
=USB_VDDA33T
USB supply initially turned
on to enable USB boot-loader
USB supply can be
independently turned off/on
VDD_CORE
=VDDCORE_ANA
=VDDAPLL
XRES
processor state
reset bootloader application program
Peripheral voltages can be started simultaneously, but because of transient currents during start-up flowing into decoupling caps it is suggested
that these voltages are turned on in a serial sequence.
The USB supply voltage should be turned on at start-up to enable start of USB loader without any needed configuration for the AFE chip.
Symbol
Parameter
Min Typ Max Unit
T1 delay between VDD_PERI
0.2
3
ms
and VDD_CORE startup
T2 delay between VDD_MEM
0.2
2
ms
and VDD_CORE startup
T3 delay between USB_VDD
0.2
1
ms
and VDD_CORE startup
T4 delay between VDD_CORE 0.01
1
ms
startup and XRES release
© 2003-2010, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
Revision 1.12
11 - 124
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AS3524.PDF ] | |
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