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PDF AS3510 Data sheet ( Hoja de datos )
| Número de pieza | AS3510 | |
| Descripción | Analog Audio Front-End | |
| Fabricantes | austriamicrosystems AG | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AS3510 (archivo pdf) en la parte inferior de esta página. Total 19 Páginas | ||
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Preliminary Datasheet AS3510
AAnnalaolgoAgudViooFicroentC-Eonddec
AASS315418089
DATA SHEET
PRELIMINARY DCAOTANFSIDHEENETTIAL
General Description
The AS3510 combines high flexibility and outstanding
performance for analog audio front-end solutions.
This codec-chip contains a high performance 18 bit digital
to analog converter. The dynamic range exceeds 95dB for
best audio quality, for multi media applications (audio
playback) within battery or line operated equipment.
An additional audio power amplifier can directly drive
external headphones or small 4Ω speakers with a power of
up to half a watt. The power-up is click- and pop-less due to
a smooth start-up circuitry. The overall distortion level is
always below 0.02%.
The microphone input amplifier contains an automatic gain
control (AGC) with a dynamic range of 40dB to generate an
amplified and compressed signal for the ADC, which
provides 14 Bit resolution at 8kHz sampling-rate.
Furthermore all necessary power management is included
such as bandgap reference and four voltage regulators. The
two 2.9V regulators are used internally (analog and digital
supply), but can also be used for external purposes as well.
The third output is designed to supply the peripheral cells
and an external digital core, and is programmable from 1.5V
to 2.5V in 5 steps (default is 2.5V). They are all powered
through a DCDC-Converter, which can work down to a
voltage of 1V. So the whole chip can work from a single
battery cell.
The fourth regulator is only used for generating the supply
voltage for the analog USB 1.1 interface circuit. It is
supplied via the USB connector. The performance of the
regulators is excellent (noise, line- and load-regulation) and
allows the direct supply of sensitive analog circuits.
Because of the internal supply and signal filtering only few
small external capacitors are required for de-coupling and
stabilising and lead to very low output noise.
The current consumption is very low and makes the chip
ideally for battery powered devices.
Key Features
On chip DCDC Converter
- 1.0 to 5.5V input voltage range
4 On-chip high performance voltage regulators
- Digital Supply, 2.9V
- Analog Supply, 2.9V
- Core Supply, 1.5 to 2.5V
- USB Transceiver Supply, 3.2V
18 Bit stereo DAC
- Dynamic range >95 dB
- THD < -85dB
- De-emphasis for 32 kHz, 44.1 kHz and 48 kHz
Stereo power audio amplifier
- Max. 2x 0.5W @ 4Ω
- Analog volume control –39dB to +3dB, 3dB steps
including mute)
- Click- and pop-less startup and power down
- Auxiliary inputs for additional audio sources
Microphone input
- 14 Bit Σ∆−ADC , 8kHz sampling rate
- Automatic gain control (AGC)
- Low power consumption
- Wide battery supply range 1.0V – 5.5V
- Standard I2S interface
- Audio sampling rates: 8, 11.025, 12, 16, 22.05, 24, 32,
44.1, and 48 kHz
- I2C control interface
- USB 1.1 front-end
- 49 Pin BGA Package
Applications
- Audio frontend for cellular phones
- Stand alone MP3 player
- CD and DVD player
- PDAs
Rev. 1v2, June 2004
CONFIDENTIAL
Page 1 of 19
1 page  
Product Brief AS3510
Functional Description
Audio DAC
Block Description
This block is the complete audio DAC delivering 93dB
dynamic range. It is comprised of a multibit sigma-delta
modulator with dither option and a switched-capacitor
analog filter. This architecture provides a high insensitivity
to clock jitter. A digital interpolation filter increases the
sample rate by a factor of 8 using 3 linear phase, half-band
filters cascaded, followed by a first order SINC interpolator
with a factor of 8. This filter eliminates the images of
baseband audio remaining only the image at 64* the input
MCLK
LRCK
SCLK
SDATA(16)
SDATA(18)
64 MCLK cycles
Left Channel
15 0
17
21
0
Figure 2 I2S Waveforms
The LRCK defines if the transferred data is for the left or
right channel (L=left).
With the rising edge of the serial clock SCLK, the
inputdata gets strobed.
The data word at SDATA is max. 18 bit with MSB first and
2nd complement coded. All I2S signals change state with
falling edge of SCLK.
code
Max. positive code
+1
0
-1
Max. negative code:
hex value
1FFFF (hex)
00001 (hex)
00000 (hex)
3FFFF (hex)
20000 (hex)
Table 4
I2S Code Values
sample rate. Optionally, a dither signal can be added that
may reduce eventual noise tones at the output. However,
the use of a multibit delta-sigma modulator already
provides extremely low noise tone energy.
Signal Description
Setting DACPD to ´1´ forces the analog section to power-
down. For Normal-Operation the I2S signals have to be
applied as shown below:
64 MCLK cycles
Right Channel
15 0
17
21
0
If the dataword length is less than 18 bit, zeros have to be
added to avoid any offset value.
The frequency of master clock MCLK has to be 128 times
the input sample rate (F(LRCK)*128) with low jitter. The
rising edge of MCLK should be separated by >10ns from
LRCK edges.
There are 2 pins needed for the generation and decoupling
of reference-voltages for the DAC. AGND is AVDD/2 and
VREF is equal to AVDD. Both pins have high output
resistance which provides a suitable lowpass filter for
these reference voltages with external capacitors of 10uF
in parallel with 100nF.
The supply lines are separate for digital DVSS / DVDD and
analog AVSS / AVDD to minimise coupling influences.
The analog output is differential stereo signal at nodes
OUTRN, OUTRP and OUTLN, OUTLP respectively.
Rev. 1v2, June 2004
CONFIDENTIAL
Page 5 of 19
5 Page 
Product Brief AS3510
Block Characteristics
Overall
SUPPLY
AVDD (AVDD = 2.9 V)
DVDD analog (DVDD = 2.9V)
IDD in Power Down
Table 13 Table of Overall Block Characteristics
AudioDAC
PARAMETER
ANALOG PERFORMANCE
THD+Noise at –1dB_FS
Dynamic Range (20Hz-20kHz, -60dBFS)
Interchannel Mismatch
Table 14 Table of AudioDAC Block Characteristics
Power Amplifier
PARAMETER
ANALOG PERFORMANCE
R_Load at AOUTR and AOUTL differential
R_Load at AOUTR and AOUTL single ended
Gain Step Precision (RLmin-max,20Hz-20kHz)
THD @ 1kHz, BVDD=3-5V, Gain=8, no Load
PSRR (200Hz-20kHz)
IOUT_powerdown
Tpower_up (Cbgnd=100nF)
Table 15 Table of Power Amplifier Block Characteristics
MIN TYP MAX UNIT
2.6 9 mA
4.5 8.5 mA
< 1 10 uA
MIN TYP MAX UNIT
-85 -75 dB
90 93
dB
0.25 dB
MIN TYP MAX UNIT
8 Ohm
4 Ohm
±0.5 ± dB
-
-
0.03%
%
60 - - dB
-20 20 uA
200 ms
Rev. 1v2, June 2004
CONFIDENTIAL
Page 11 of 19
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet AS3510.PDF ] | |
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