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PDF ET4344 Data sheet ( Hoja de datos )
| Número de pieza | ET4344 | |
| Descripción | 10-pin 24-Bit 192kHz Stereo D/A Converter | |
| Fabricantes | Etek Microelectronics | |
| Logotipo |  |
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Etek
Microelectronics
ET4344
10-pin, 24-Bit, 192kHz Stereo D/A Converter
General Description
The ET4344 family members are complete, stereo digital-to-analog output systems including
interpolation,multi-bit D/A conversion and output analog filtering in a 10-pin package. The ET4344/5/6/8 support
all major audio data interface formats, and the individual devices differ only in the supported interface format.
The ET4344 family is based on a fourth order multi-bit delta-sigma modulator with a linear analog low-pass
filter. This family also includes auto-speed mode detection using both sample rate and master clock ratioas a
method of auto-selecting sampling rates between 2kHz and 200kHz.
The ET4344 family contains on-chip digital de-emphasis, operates from a single +3.3V or +5V power supply,
and requires minimal support circuitry. These features are ideal for DVD players & recorders, digital televisions,
home theater and set top box products, and automotive audio systems.
The ET4344 family is available in a 10-pin MSOP package in both Commercial (-10 to +85 °C) and
Automotive grades (-40 to +85 °C).
Features
z Multi-bit Delta-Sigma Modulator
z 24-bit Conversion
z Automatically Detects Sample Rates up to 192kHz.
z 105 dB Dynamic Range
z -90 dB THD+N
z Low Clock-Jitter Sensitivity
z Single +3.3V or +5V Power Supply
z Filtered Line-Level Outputs
z On-chip Digital De-emphasis
z Popguard™ Technology
z Package：MSOP10（ET4344U）
Rev 1.0 2009-02-27
1/16
1 page  
ET4344
Internal SCLK Mode
Right Justified, 24-Bit Data
INT SCLK = 64 Fs if
MCLK/LRCK = 1024, 512, 256, 128, or 64
INT SCLK = 48 Fs if
MCLK/LRCK = 768, 384, 192, or 96
External SCLK Mode
Right Justified, 24-Bit Data
Data Valid on Rising Edge of SCLK
SCLK Must Have at Least 48 Cycles per LRCK Period
INT SCLK = 72 Fs if MCLK/LRCK = 1152
Figure 3. ET4346 Data Format (Right Justified 24)
Internal SCLK Mode
Right Justified, 16-Bit Data
INT SCLK = 32 Fs if
MCLK/LRCK = 1024, 512, 256, 128, or 64
INT SCLK = 48 Fs if
MCLK/LRCK = 768, 384, 192, or 96
External SCLK Mode
Right Justified, 16-Bit Data
Data Valid on Rising Edge of SCLK
SCLK Must Have at Least 32 Cycles per LRCK Period
INT SCLK = 72 Fs if MCLK/LRCK = 1152
Figure 4. ET4348 Data Format (Right Justified 16)
De-Emphasis
The ET4344 family includes on-chip digital de-emphasis. Figure 5 shows the de-emphasis curve for Fs equal
to 44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in sample
rate, Fs.
The de-emphasis filter is active (inactive) if the DEM /SCLK pin is low (high) for 5 consecutive falling
edges of LRCK. This function is available only in the internal serial clock mode
Rev 1.0 2009-02-27
5/16
5 Page 
ET4344
-20 dB
- -82 -72 - -80 -70 dB
-60 dB
- -42 -32 - -40 -30 dB
16-Bit
0 dB - -90 -82 - -90 -82 dB
-20 dB
- -73 -63 - -73 -63 dB
-60 dB
- -33 -23 - -33 -23 dB
Notes: 1.One-half LSB of triangular PDF dither added to data.
DAC ANALOG CHARACTERISTICS - ALL MODES
Parameter
Interchannel Isolation (1 kHz)
Symbol
Min
Typ
Max Unit
- 100 - dB
DC Accuracy
Interchannel Gain Mismatch
Gain Drift
- 0.1 0.25 dB
- 100 - ppm/°C
Analog Output
Full Scale Output Voltage
0.60•VA 0.65•VA 0.70•VA Vpp
Quiescent Voltage
VQ - 0.5•VA - VDC
Max DC Current draw from an AOUT pin
IOUTmax
-
10
- μA
Max Current draw from VQ
IQmax
-
100
- μA
Max AC-Load Resistance(see Figure 20) RL - 3 - kΩ
Max Load Capacitance(see Figure 20)
CL - 100 - pF
Output Impedance
ZOUT
-
100
-
Ω
COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
(The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired
sample rate by multiplying the given characteristic by Fs.) See (Note 6)
Parameter
Symbol Min Typ Max Unit
Combined Digital and On-chip Analog Filter ResponseSingle-Speed Mode
Passband (Note 2)
to -0.1 dB corner
0
to -3 dB corner
0
Frequency Response 10 Hz to 20 kHz
-.175
StopBand
.5465
StopBand Attenuation(Note 3)
50
Group Delay
tgd -
De-emphasis Error (Note 5)
Fs = 32 kHz
-
Fs = 44.1 kHz
-
Fs = 48 kHz
-
-
-
-
-
-
10/Fs
-
-
-
.35
.4992
+.01
-
-
-
+1.5/+0
+.05/-.25
-.2/-.4
Fs
Fs
dB
Fs
dB
s
dB
dB
dB
Combined Digital and On-chip Analog Filter ResponseDouble-Speed Mode
Passband (Note 2)
to +0.1 dB corner
0 - .22 Fs
to -3 dB corner
0 - .501 Fs
Frequency Response 10 Hz to 20 kHz
-.15 - +.15 dB
StopBand
.5770
-
- Fs
StopBand Attenuation (Note 3)
55 - - dB
Group Delay
tgd - 5/Fs - s
11/16
Rev 1.0 2009-02-27
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ET4344.PDF ] | |
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