PDF LTC691 Data sheet ( Hoja de datos )

Número de pieza	LTC691
Descripción	Microprocessor Supervisory Circuits
Fabricantes	Linear Technology
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No Preview Available ! Features n Guaranteed Reset Assertion at VCC = 1V n 1.5mA Maximum Supply Current n Fast (35ns Max) Onboard Gating of RAM Chip Enable Signals n SO-8 and S16 Packaging n 4.65V Precision Voltage Monitor n Power OK/Reset Time Delay: 50ms, 200ms or Adjustable n Minimum External Component Count n 1µA Maximum Standby Current n Voltage Monitor for Power-Fail or Low Battery Warning n Thermal Limiting n Performance Specified Over Temperature n Superior Upgrade for MAX690 Family Applications n Critical µP Power Monitoring n Intelligent Instruments n Battery-Powered Computers and Controllers n Automotive Systems LTC690/LTC691 LTC694/LTC695 Microprocessor Supervisory Circuits Description The LTC®690 family, LTC690/LTC691/LTC694/LTC695, provides complete power supply monitoring and battery control functions for microprocessor reset, battery back- up, CMOS RAM write protection, power failure warning and watchdog timing. A precise internal voltage reference and comparator circuit monitor the power supply line. When an out-of-tolerance condition occurs, the reset outputs are forced to active states and the chip enable output unconditionally write-protects external memory. In addition, the RESET output is guaranteed to remain logic low even with VCC as low as 1V. The LTC690 family powers the active CMOS RAMs with a charge pumped NMOS power switch to achieve low drop out and low supply current. When primary power is lost, auxiliary power, connected to the battery input pin, powers the RAMs in standby through an efficient PMOS switch. For an early warning of impending power failure, the LTC690 family provides an internal comparator with a user-defined threshold. An internal watchdog timer is also available, which forces the reset pins to active states when the watchdog input is not toggled prior to a preset timeout period. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Typical Application VIN ≥ 7.5V + 10µF LT®1086-5 VIN VOUT ADJ 5V + 100µF 51k 10k 0.1µF 3V VCC VOUT LTC690/LTC691 LTC694/LTC695 VBATT RESET PFO PFI GND WDI MICROPROCESSOR RESET, BATTERY BACK-UP, POWER FAILURE WARNING AND WATCHDOG TIMING ARE ALL IN A SINGLE CHIP FOR MICROPROCESSOR SYSTEMS 0.1µF POWER TO µP CMOS RAM POWER µP SYSTEM µP RESET µP NMI I/O LINE 0.1µF 100Ω 690 TA01 For more information www.linear.com/690 RESET Output Voltage vs Supply Voltage 5 TA = 25°C EXTERNAL PULL-UP = 10µA 4 VBATT = 0V 3 2 1 0 01 2 345 SUPPLY VOLTAGE (V) 690 TA02 690ff 1 1 page LTC690/LTC691 LTC694/LTC695 E lectrical Characteristics The l denotes specifications which apply over the operating temperature range, otherwise specifications are at TA = 25°C. VCC = full operating range, VBATT = 2.8V, unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS RESET, RESET, WDO, LOWLINE Output Short-Circuit Current (Note 4) Output Source Current Output Sink Current 1 3 25 µA 25 mA WDI Input Threshold Logic Low Logic high 0.8 V 3.5 WDI Input Current WDI = VOUT WDI = 0V l l –50 4 –8 50 µA Power-Fail Detector PFI Input Threshold PFI Input Threshold PSRR VCC = 5V l 1.25 1.3 1.35 V 0.3 mV/V PFI Input Current ±0.01 ±25 nA PFO Output Voltage (Note 4) PFO Short-Circuit Source Current (Note 4) IISSIONUKR=CE3=.21mµAA PFI = HIGH, PFO = 0V 0.4 3.5 1 3 25 V µA PFI Comparator Response Time (Falling) PFI Comparator Response Time (Rising) (Note 4) PFI = LOW, PFO = VOUT ∆VIN = –20mV, VOD = 15mV ∆VIN = 20mV, VOD = 15mV with 10kΩ Pull-Up 25 mA 2 µs 40 µs 8 Chip Enable Gating CE IN Threshold CE IN Pull-Up Current (Note 7) VIL VIH 0.8 V 2 3 µA CE OUT Output Voltage CE Propagation Delay ISINK = 3.2mA ISOURCE = 3.0mA ISOURCE = 1µA, VCC = 0V VCC = 5V, CL = 20pF VOUT – 1.50 VOUT – 0.05 l 20 20 0.4 35 45 V ns CE OUT Output Short-Circuit Current Output Source Current Output Sink Current 30 mA 35 Oscillator OSC IN Input Current (Note 7) ±2 µA OSC SEL Input Pull-Up Current (Note 7) 5 µA OSC IN Frequency Range OSC SEL = 0V l0 250 kHz OSC IN Frequency with External Capacitor OSC SEL = 0V, COSC = 47pF 4 kHz Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND. Note 3: For military temperature range parts or for the LTC692 and LTC693, consult the factory. Note 4: The output pins of BATT ON, LOWLINE, PFO, WDO, RESET and RESET have weak internal pull-ups of typically 3µA. However, external pull-up resistors may be used when higher speed is required. Note 5: The LTC690 and LTC691 have minimum reset active time of 35ms (50ms typically) while the LTC694 and LTC695 have longer minimum reset active time of 140ms (200ms typically). The reset active time of the LTC691 and LTC695 can be adjusted (see Table 2 in Applications Information section). Note 6: The external clock feeding into the circuit passes through the oscillator before clocking the watchdog timer (See Block Diagram). Variation in the timeout period is caused by phase errors which occur when the oscillator divides the external clock by 64. The resulting variation in the timeout period is 64 clocks plus one clock of jitter. Note 7: The input pins of CE IN, OSC IN and OSC SEL have weak internal pull-ups which pull to the supply when the input pins are floating. For more information www.linear.com/690 690ff 5 5 Page LTC690/LTC691 LTC694/LTC695 Applications Information If battery connections are made through long wires, a 10Ω to 100Ω series resistor and a 0.1µF capacitor are recommended to prevent any overshoot beyond VCC due to the lead inductance (Figure 4). 10Ω 4.3M 0.1µF VBATT LTC690 LTC691 LTC694 LTC695 GND 690 F04 Figure 4. 10Ω/0.1µF Combination Eliminates Inductive Overshoot and Prevents Spurious Resets During Battery Replacement Table 1 shows the state of each pin during battery back-up. When the battery switchover section is not used, connect VBATT to GND and VOUT to VCC. Memory Protection The LTC691 and LTC695 include memory protection cir- cuitry that ensures the integrity of the data in memory by preventing write operations when VCC is at invalid level. Two additional pins, CE IN and CE OUT, control the Chip Enable or Write inputs of CMOS RAM. When VCC is 5V, CE OUT follows CE IN with a typical propagation delay of 20ns. When VCC falls below the reset voltage threshold or VBATT, CE OUT is forced high, independent of CE IN. CE OUT is an alternative signal to drive the CE, CS, or Write input of battery-backed up CMOS RAM. CE OUT can also be used to drive the Store or Write input of an EEPROM, EAROM or NOVRAM to achieve similar protection. Figure 5 shows the timing diagram of CE IN and CE OUT. CE IN can be derived from the microprocessor’s address decoder output. Figure 6 shows a typical nonvolatile CMOS RAM application. Memory protection can also be achieved with the LTC690 and LTC694 by using RESET as shown in Figure 7. Table 1. Input and Output Status in Battery Back-Up Mode SIGNAL STATUS VCC VOUT VBATT BATT ON PFI C2 monitors VCC for active switchover. VOUT is connected to VBATT through an internal PMOS switch. The supply current is 1µA maximum. Logic high. The open-circuit output voltage is equal to VOUT. Power failure input is ignored. PFO Logic low RESET Logic low RESET Logic high. The open-circuit output voltage is equal to VOUT. LOWLINE Logic low WDI Watchdog input is ignored. WDO CE IN Logic high. The open-circuit output voltage is equal to VOUT. ChipEnable Input is ignored. CE OUT OSC IN Logic high. The open-circuit output voltage is equal to VOUT. OSC IN is ignored. OSC SEL OSC SEL is ignored. V2 VCC V1 V1 = RESET VOLTAGE THRESHOLD V2 = RESET VOLTAGE THRESHOLD + RESET THRESHOLD HYSTERESIS CE IN CE OUT VOUT = VBATT Figure 5. Timing Diagram for CE IN and CE OUT For more information www.linear.com/690 VOUT = VBATT 690 F05 690ff 11 11 Page

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