PDF ADE7978 Data sheet ( Hoja de datos )

Número de pieza	ADE7978
Descripción	Isolated Energy Metering Chipset
Fabricantes	Analog Devices
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No Preview Available ! Data Sheet Isolated Energy Metering Chipset for Polyphase Shunt Meters ADE7978/ADE7933/ADE7932 FEATURES Enables shunt current sensors in polyphase energy meters Immune to magnetic tampering Highly accurate; supports EN 50470-1, EN 50470-3, IEC 62053-21, IEC 62053-22, IEC 62053-23, ANSI C12.20, and IEEE 1459 standards Compatible with 3-phase, 3- or 4-wire (delta or wye) meters and other 3-phase services Computes active, reactive, and apparent energy on each phase and on the overall system Less than 0.2% error in active and reactive energy over a dynamic range of 2000 to 1 at TA = 25°C Less than 0.1% error in voltage rms over a dynamic range of 500 to 1 at TA = 25°C Less than 0.25% error in current rms over a dynamic range of 500 to 1 at TA = 25°C Power quality measurements including THD Single 3.3 V supply Operating temperature: −40°C to +85°C Flexible I2C, SPI, and HSDC serial interfaces Safety and regulatory approvals (pending) UL recognition 5000 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice #5A IEC 61010-1: 400 V rms VDE certificate of conformity DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 846 V peak APPLICATIONS Shunt-based polyphase meters Power quality monitoring Solar inverters Process monitoring Protective devices Isolated sensor interfaces Industrial PLCs TYPICAL APPLICATION CIRCUIT PHASE PHASE PHASE NEUTRAL A B C ISOLATION BARRIER V1P VM IM PHASE A ADE7932/ IP ADE7933 V2P 3.3V GNDISO_A GNDMCU V1P VM IM PHASE B ADE7932/ IP ADE7933 V2P 3.3V GNDISO_B GNDMCU V1P VM IM PHASE C ADE7932/ IP ADE7933 V2P 3.3V ADE7978 ENERGY METERING IC 3.3V I2C/HSDC OR SPI IRQ0, IRQ1 GNDMCU 3.3V GNDMCU LOAD GNDISO_C GNDMCU V1P VM NEUTRAL IM LINE ADE7932/ ADE7933 IP (OPTIONAL) V2P 3.3V GNDISO_N GNDMCU EARTH Figure 1. 3-Phase, 4-Wire Meter with Four ADE7933/ADE7932 Devices and One ADE7978 1 Protected by U.S. Patents 5,952,849; 6,873,065; 7,075,329; 6,262,600; 7,489,526; and 7,558,080. Other patents are pending. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page Data Sheet FUNCTIONAL BLOCK DIAGRAMS RESET 12 VDD GND LDO DGND 21 20 22 23 POR LDO ADE7978/ADE7933/ADE7932 ADE7978 XTALIN 25 XTALOUT 24 VT_B 1 DATA_B 2 RESET_EN 3 CLKOUT 4 SYNC 5 VT_C 6 DATA_C 7 VT_N 8 DATA_N 9 VT_A 27 DATA_A 28 AV2GAIN HPFEN BIT AV2RMSOS 27 DIGITAL BLOCK HPF X2 LPF SELECTION BIT VB/TEMP SENSOR 211 ATGAIN ATEMPOS AIGAIN HPFEN BIT ATEMP0 TEMPCO 1 AV2RMS ATEMP AIRMSOS X2 LPF X2 LPF AVRMSOS AIRMS APGAIN AVRMS HPF APGAIN AWATTOS APHCAL HPFEN BIT HPF AV1GAIN ACTIVE/REACTIVE/APPARENT TOTAL ENERGIES AND VOLTAGE/CURRENT RMS CALCULATION FOR PHASE B (SEE PHASE A FOR DETAILED DATAPATH) ACTIVE/REACTIVE/APPARENT TOTAL ENERGIES AND VOLTAGE/CURRENT RMS CALCULATION FOR PHASE C (SEE PHASE A FOR DETAILED DATAPATH) NTEMP LPF APGAIN AVAROS COMPUTATIONAL BLOCK FOR TOTAL REACTIVE POWER APGAIN AFWATTOS PHASE A, PHASE B, PHASE C DATA COMPUTATIONAL BLOCK FOR FUNDAMENTAL ACTIVE AND REACTIVE POWER APGAIN AFVAROS TEMPCO DIGITAL SIGNAL PROCESSOR NIGAIN HPFEN BIT NTEMP0 1 HPF NIRMSOS X2 LPF NIRMS CF1DEN :DFC 13 CF1 CF2DEN DFC : CF3DEN 14 CF2 :DFC 15 CF3/HSCLK SPI OR I2C AND HSDC 26 ZX/DREADY 10 IRQ0 11 IRQ1 17 SCLK/SCL 19 MOSI/SDA 18 MISO/HSD 16 SS/HSA Figure 2. ADE7978 Functional Block Diagram Rev. 0 \| Page 5 of 120 5 Page Data Sheet ADE7978/ADE7933/ADE7932 SPI Interface Timing Parameters VDD = 3.3 V ± 10%, GND = DGND = 0 V, XTALIN = 16.384 MHz, TMIN to TMAX = −40°C to +85°C. Table 4. Parameter SS to SCLK Edge SCLK Period SCLK Low Pulse Width SCLK High Pulse Width Data Output Valid After SCLK Edge Data Input Setup Time Before SCLK Edge Data Input Hold Time After SCLK Edge Data Output Fall Time Data Output Rise Time SCLK Rise Time SCLK Fall Time MISO Disable After SS Rising Edge SS High After SCLK Edge Symbol tSS tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tDIS tSFS Min 50 0.4 175 175 100 50 100 Max 40001 130 20 20 20 20 1 Unit ns μs ns ns ns ns ns ns ns ns ns μs ns 1 Guaranteed by design. SS tSS tSFS SCLK tDAV tSL tSH tSF tSR tDIS MISO MSB INTERMEDIATE BITS LSB MOSI tDF INTERMEDIATE BITS tDR tDSU MSB IN tDHD Figure 6. SPI Interface Timing LSB IN Rev. 0 \| Page 11 of 120 11 Page

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