PDF MC14508B Data sheet ( Hoja de datos )

Número de pieza	MC14508B
Descripción	Dual 4-Bit Latch
Fabricantes	Motorola Semiconductors
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No Preview Available ! MOTOROLA SEMICONDUCTOR TECHNICAL DATA Dual 4-Bit Latch The MC14508B dual 4–bit latch is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. The part consists of two identical, independent 4–bit latches with separate Strobe (ST) and Master Reset (MR) controls. Separate Disable inputs force the outputs to a high impedance state and allow the devices to be used in time sharing bus line applications. These complementary MOS latches find primary use in buffer storage, holding register, or general digital logic functions where low power dissipation and/or high noise immunity is desired. • 3–State Output • Supply Voltage Range = 3.0 Vdc to 18 Vdc ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ• Capable–of Driving Two Low–power TTL Loads or One Low–power Schottky TTL Load over the Rated Temperature Range ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMAXIMUM RATINGS* (Voltages Referenced to VSS) Symbol Parameter Value Unit VDD Vin, Vout Iin, Iout DC Supply Voltage Input or Output Voltage (DC or Transient) Input or Output Current (DC or Transient), per Pin – 0.5 to + 18.0 – 0.5 to VDD + 0.5 ± 10 V V mA PD Power Dissipation, per Package† Tstg Storage Temperature 500 – 65 to + 150 mW _C TL Lead Temperature (8–Second Soldering) 260 _C * Maximum Ratings are those values beyond which damage to the device may occur. †Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C TRUTH TABLE MR ST Disable D3 D2 D1 D0 Q3 Q2 Q1 Q0 01 0 00000000 01 0 00010001 01 0 00100010 01 0 01000100 01 0 10001000 0 0 0 XXXX Latched 1X 0 XXXX0 0 0 0 XX 1 XXXX High Impedance X = Don’t Care DIS CIRCUIT DIAGRAM VDD MR ST Dn Qn MC14508B L SUFFIX CERAMIC CASE 623 P SUFFIX PLASTIC CASE 709 DW SUFFIX SOIC CASE 751E ORDERING INFORMATION MC14XXXBCP MC14XXXBCL MC14XXXBDW Plastic Ceramic SOIC TA = – 55° to 125°C for all packages. BLOCK DIAGRAM 1 MR Q0 2 ST 3 DIS Q1 4 D0 6 D1 Q2 8 10 D2 D3 Q3 5 7 9 11 13 MR Q0 17 14 ST 15 DIS Q1 19 16 D0 18 D1 Q2 21 20 22 D2 D3 Q3 23 VDD = PIN 24 VSS = PIN 12 (TO OTHER THREE LATCHES) REV 3 1/94 ©MMCot1or4o5la0, I8nBc. 1995 344 VSS MOTOROLA CMOS LOGIC DATA 1 page 3–STATE MODE OF OPERATION The MC14508B can be used in bussed systems as shown. The output terminals of N 4–bit latches can be directly wired to a bus line, and to one of the 4–bit latches selected. The selected latch controls the logic state of the bus line and the remaining (N–1) 4–bit latches are disabled into a high imped- ance “off” state. The number of latches, N, which may be connected to a bus line is determined from the output drive current, IOD, the 3–state or disabled output leakage current, ITL, and the load current, IL, required to drive the bus line (in- cluding fanout to other device inputs) and can be calculated by the following: N = IOD – IL + 1 ITL N must be calculated for both high and low logic states of the bus line. IOD SELECTED AS 1/2 DRIVING DEVICE MC14508B IOD 1/2 DISABLED MC14508B ITL ITL DISABLED 1/2 MC14508B ITL TYPICAL 3–STATE APPLICATIONS EXAMPLE 1 RESET CLOCK SERIAL DATA MC14015B 4–BIT SHIFT 4–BIT SHIFT REGISTER REGISTER STROBE DISABLE MC QUAD LATCH 14508B (3–STATE) QUAD LATCH (3–STATE) DISABLE 4–LINE DATA BUS ITL IL BUS LINES IL EXAMPLE 2 3–STATE 4–BIT LATCH 3–STATE 4–BIT LATCH MC 14508B MC 14508B 4–LINE DATA BUS 4–LINE DATA BUS 3–STATE 4–BIT LATCH 3–STATE 4–BIT LATCH DATA BUS MC14519B A B MC14508B 348 MOTOROLA CMOS LOGIC DATA 5 Page

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