STU4N80K5 Datasheet PDF - STMicroelectronics
| Part Number | STU4N80K5 | |
| Description | N-CHANNEL MOSFET | |
| Manufacturers | STMicroelectronics | |
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STD4N80K5, STF4N80K5,
STP4N80K5, STU4N80K5
N-channel 800 V, 2.1 Ω typ., 3 A Zener-protected SuperMESH™ 5
Power MOSFETs in DPAK, TO-220FP, TO-220 and IPAK packages
Datasheet - production data
TAB
3
1
DPAK
TAB
3
2
1
TO-220FP
TAB
3
2
1
TO-220
IPAK
3
2
1
Figure 1. Internal schematic diagram
' 7$%
Features
Order codes VDS RDS(on) max ID
STD4N80K5
STF4N80K5
800 V
STP4N80K5
2.5 Ω
3A
STU4N80K5
• Outstanding RDS(on) * area
• Worldwide best FOM (figure of merit)
• Ultra low gate charge
• 100% avalanche tested
• Zener-protected
PTOT
60 W
20 W
60 W
Applications
• Switching applications
*
6
AM01476v1
Description
These N-channel Zener-protected Power
MOSFETs are designed using ST’s revolutionary
avalanche-rugged very high voltage
SuperMESH™ 5 technology, based on an
innovative proprietary vertical structure. The
result is a dramatic reduction in on-resistance,
and ultra-low gate charge for applications which
require superior power density and high
efficiency.
Order code
STD4N80K5
STF4N80K5
STP4N80K5
STU4N80K5
Table 1. Device summary
Marking
Packages
4N80K5
DPAK
TO-220FP
TO-220
IPAK
Packaging
Tape and reel
Tube
December 2013
This is information on a product in full production.
DocID025105 Rev 2
1/23
www.st.com
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STD4N80K5, STF4N80K5, STP4N80K5, STU4N80K5
Electrical characteristics
Symbol
Table 6. Switching times
Parameter
Test conditions
td(on)
tr
td(off)
tf
Turn-on delay time
Rise time
Turn-off-delay time
Fall time
VDD = 400 V, ID = 1.5 A,
RG = 4.7 Ω, VGS = 10 V
(see Figure 18)
Min. Typ. Max. Unit
- 16.5 - ns
- 15 - ns
- 36 - ns
- 21 - ns
Symbol
Table 7. Source drain diode
Parameter
Test conditions
ISD
(1)
ISDM
(2)
VSD
Source-drain current
Source-drain current (pulsed)
Forward on voltage
ISD = 3 A, VGS = 0
trr
Qrr
IRRM
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD = 3 A, di/dt = 100 A/μs
VDD= 60 V TJ = 25 °C
(see Figure 20)
trr
Qrr
IRRM
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD = 3 A, di/dt = 100 A/μs
VDD= 60 V TJ = 150 °C
(see Figure 20)
1. Pulse width limited by safe operating area
2. Pulsed: pulse duration = 300 μs, duty cycle 1.5%
Min. Typ. Max. Unit
- 3A
12 A
- 1.5 V
- 242
ns
- 1.42
μC
- 12
A
- 373
ns
- 1.98
μC
- 10.5
A
Symbol
Table 8. Gate-source Zener diode
Parameter
Test conditions
Gate-source breakdown
V(BR)GSO voltage
IGS= ± 1 mA, ID=0
Min. Typ. Max. Unit
30 - V
The built-in back-to-back Zener diodes have specifically been designed to enhance not only
the device’s ESD capability, but also to make them safely absorb possible voltage transients
that may occasionally be applied from gate to source. In this respect the Zener voltage is
appropriate to achieve an efficient and cost-effective intervention to protect the device’s
integrity. These integrated Zener diodes thus avoid the usage of external components.
DocID025105 Rev 2
5/23
23
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| Information | Total 23 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
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