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PDF MSM82C53-2GS Data sheet ( Hoja de datos )
| Número de pieza | MSM82C53-2GS | |
| Descripción | CMOS PROGRAMMABLE INTERVAL TIMER | |
| Fabricantes | OKI | |
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E2O0018-27-X2
¡ Semiconductor¡ Semiconductor
MThSiMs v8e2rCsi5o3n-:2JRaSn/. G19S9/8JS
Previous version: Aug. 1996
MSM82C53-2RS/GS/JS
CMOS PROGRAMMABLE INTERVAL TIMER
GENERAL DESCRIPTION
The MSM82C53-2RS/GS/JS is programmable universal timers designed for use in
microcomputer systems. Based on silicon gate CMOS technology, it requires a standby current
of only 100 mA (max.) when the chip is in the nonselected state. During timer operation, power
consumption is still very low only 8 mA (max.) at 8 MHz of current required.
The device consists of three independent counters, and can count up to a maximum of 8 MHz
(MSM82C53-2). The timer features six different counter modes, and binary count/BCD count
functions. Count values can be set in byte or word units, and all functions are freely
programmable.
FEATURES
• Maximum operating frequency of 8 MHz (MSM82C53-2)
• High speed and low power consumption achieved through silicon gate CMOS technology
• Completely static operation
• Three independent 16-bit down-counters
• 3 V to 6 V single power supply
• Six counter modes available for each counter
• Binary and decimal counting possible
• 24-pin Plastic DIP (DIP24-P-600-2.54): (Product name: MSM82C53-2RS)
• 28-pin Plastic QFJ (QFJ28-P-S450-1.27): (Product name: MSM82C53-2JS)
• 32-pin Plastic SSOP(SSOP32-P-430-1.00-K): (Product name: MSM82C53-2GS-K)
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1 page  
¡ Semiconductor
MSM82C53-2RS/GS/JS
AC CHARACTERISTICS
(VCC = 4.5 V to 5.5 V, Ta = –40 to +85°C)
Parameter
Address Set-up Time before Reading
Address Hold Time after Reading
Read Pulse Width
Read Recovery Time
Address Set-up Time before Writing
Address Hold Time after Writing
Write Pulse Width
Data Input Set-up Time before Writing
Data Input Hold Time after Writing
Write Recovery Time
Clock Cycle Time
Clock "H" Pulse Width
Clock "L" Pusle Width
"H" Gate Pulse Width
"L" Gate PUlse Width
Gate Input Set-up Time before Clock
Gate Input Hold Time after Clock
Output Delay Time after Reading
Output Floating Delay Time after
Reading
Output Delay Time after Gate
Output Delay Time after Clock
Output Delay Time after Address
Symbol
tAR
tRA
tRR
tRVR
tAW
tWA
tWW
tDW
tWD
tRVW
tCLK
tPWH
tPWL
tGW
tGL
tGS
tGH
tRD
tDF
tODG
tOD
tAD
MSM82C53-2
Min.
30
0
150
200
0
20
150
100
20
200
125
60
60
50
50
50
50
—
Max.
—
—
—
—
—
—
—
—
—
—
D.C.
—
—
—
—
—
—
120
5 90
— 120
— 150
— 180
Unit Condition
ns
ns Read
ns Cycle
ns
ns
ns
ns Write
ns Cycle
ns
ns
ns CL = 150 pF
ns
ns Clock
ns and
ns Gate
ns Timing
ns
ns
ns
ns Delay
ns Time
ns
Note: Timing measured at VL = 0.8 V and VH = 2.2 V for both inputs and outputs.
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¡ Semiconductor
MSM82C53-2RS/GS/JS
Mode Definition
• Mode 0 (terminal count)
The counter output is set to “L” level by the mode setting. If the count value is then written
in the counter with the gate input at “H” level (that is, upon completion of writing the MSB
when there are two bytes), the clock input counting is started. When the terminal count is
reached, the output is switched to “H” level and is maintained in this status until the control
word and count value are set again.
Counting is interrupted if the gate input is switched to “L” level, and restarted when switched
back to “H” level.
When Count Values are written during counting, the operation is as follows:
1-byte Read/Load. ............ When the new count value is written, counting is stopped
immediately, and then restarted at the new count value by the next
clock.
2-byte Read/Load ............. When byte 1 (LSB) of the new count value is written, counting is
stopped immediately. Counting is restarted at the new count
value when byte 2 (MSB) is written.
• Mode 1 (programmable one-shot)
The counter output is switched to “H” level by the mode setting. Note that in this mode,
counting is not started if only the count value is written. Since counting has to be started in
this mode by using the leading edge of the gate input as a trigger, the counter output is
switched to “L” level by the next clock after the gate input trigger. This “L” level status is
maintained during the set count value, and is switched back to “H” level when the terminal
count is reached.
Once counting has been started, there is no interruption until the terminal count is reached,
even if the gate input is switched to “L” level in the meantime. And although counting
continues even if a new count value is written during the counting, counting is started at the
new count value if another trigger is applied by the gate input.
• Mode 2 (rate generator)
The counter output is switched to “H” level by the mode setting. When the gate input is at
“H” level, counting is started by the next clock after the count value has been written. And
if the gate input is at “L” level, counting is started by using the rising edge of the gate input
as a trigger after the count value has been set.
An “L” level output pulse appears at the counter output during a single clock duration once
every n clock inputs where n is the set count value. If a new count value is written during
while counting is in progress, counting is started at the new count value following output of
the pulse currently being counted. And if the gate input is switched to “L” level during
counting, the counter output is forced to switch to “H” level, the counting being restarted by
the rising edge of the gate input.
• Mode 3 (square waveform rate generator)
The counter output is switched to “H” level by the mode setting. Counting is started in the
same way as described for mode 2 above.
The repeated square wave output appearing at the counter output contains half the number
of counts as the set count value. If the set count value (n) is an odd number, the repeated square
wave output consists of only (n+1)/2 clock inputs at “H” level and (n-1)/2 clock inputs at “L”
level.
If a new count value is written during counting, the new count value is reflected immediately
after the change (“H” to “L” or “L” to “H”) in the next counter output to be executed. The
counting operation at the gate input is done the same as in mode 2.
11/19
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