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PDF Si4712 Data sheet ( Hoja de datos )

Número de pieza Si4712
Descripción FM RADIO TRANSMITTER
Fabricantes Silicon Laboratories 
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Si4712/13-B30
FM RADIO TRANSMITTER WITH RECEIVE POWER SCAN
Features
Integrated receive power
measurement
Worldwide FM band support
(76–108 MHz)
Requires only two external
components
Frequency synthesizer with
integrated VCO
Digital stereo modulator
Programmable pre-emphasis
Analog/digital audio interface
Audio silence detector
Programmable reference clock
RDS/RBDS encoder (Si4713 only)
PCB loop and stub antenna
support with self-calibrated
capacitor tuning
Programmable transmit level
Audio dynamic range control
Advanced modulation control
2.7 to 5.5 V supply voltage
Integrated LDO regulator
3 x 3 x 0.55 mm 20-pin QFN
Pb-free and RoHS Compliant
Designed for compatibility with
cellular operation
Applications
Cellular handsets/hands-free
MP3 players
Portable media players
Wireless speakers/microphone
Satellite digital audio radios
Personal computers/notebooks
Description
The Si4712/13-B30 integrates the complete transmit functions for
standards-compliant unlicensed FM broadcast stereo transmission. The
chip also allows integrated receive power scanning to identify low signal
power FM channels. Users must comply with local regulations on radio
frequency (RF) transmission.
Functional Block Diagram
Si4712/13
Ordering Information:
See page 34.
Pin Assignments
Si4712/13-B30
(Top View)
NC 1 20 19 18 17 16
NC 2
15 RIN
RFGND 3
TXO 4
GND
PAD
14 DFS
13 DIN
RST 5
12 GND
6 7 8 9 10 11 VDD
Tx
Ant TXO
L1
120 nH
RFGND
PEAK
DETECT
DIGITAL
AUDIO
DSP
DAC ADC
DAC ADC
DIN
DFS
LIN
RIN
Patents pending
Note: To ensure proper operation and
performance, follow the guide-
lines in “AN383: Universal
Antenna Selection and Layout
Guidelines.” Silicon Laboratories
will evaluate schematics and lay-
outs for qualified customers.
VDD 2.7–5.5 V
AFC
CONTROL
INTERFACE
GPO
RDS (Si4713)
LDO
GND C1
22 nF
Rev. 1.1 2/08
Copyright © 2008 by Silicon Laboratories
Si4712/13-B30

1 page




Si4712 pdf
Si4712/13-B30
Table 3. DC Characteristics
Test conditions: VRF = 118 dBµV, stereo, Δf = 68.25 kHz, Δfpilot = 6.75 kHz, REFCLK = 32.768 kHz, unless otherwise specified.
Production test conditions: VDD = 3.3 V, VIO = 3.3 V, TA = 25 °C, FRF = 98 MHz.
Characterization test conditions: VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C, FRF = 76–108 MHz.
Parameter
Symbol Test Condition
Min Typ Max Unit
FM Transmitter from Line Input
TX Supply Current
ITX
TX Interface Supply Current
IIO
FM Transmitter from Digital Audio Input
— 18.8 22.8 mA
— 320 600 µA
TX Supply Current
IDTX DCLK = 3.072 MHz
TX Interface Supply Current
IDIO DCLK = 3.072 MHz
FM Transmitter in Receive Power Scan Mode
18.3
320
— mA
— µA
RX Supply Current
RX Interface Supply Current
Supplies and Interface
IRX
IIO
— 16.8 — mA
— 320 — µA
VDD Powerdown Current
IDD Powerdown mode
10
VIO Interface Powerdown Current IIO
SCLK, RCLK inactive
Powerdown mode
3
High Level Input Voltage1
Low Level Input Voltage1
High Level Input Current1
Low Level Input Current1
High Level Output Voltage2
Low Level Output Voltage2
VIH
VIL
IIH
IIL
VOH
VOL
VIN = VIO = 3.6 V
VIN = 0 V, VIO = 3.6 V
IOUT = 500 µA
IOUT = –500 µA
0.7 x VIO
–0.3
–10
–10
0.8 x VIO
Notes:
1. For input pins SCLK, SEN, SDIO, RST, RCLK, DCLK, DFS, DIN, GPO1, GPO2/INT, and GPO3.
2. For output pins SDIO, GPO1, GPO2/INT, and GPO3.
20
10
VIO + 0.3
0.3 x VIO
10
10
0.2 x VIO
µA
µA
V
V
µA
µA
V
V
Rev. 1.1
5

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Si4712 arduino
Si4712/13-B30
Table 8. Digital Audio Interface Characteristics
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol Test Condition Min
Typ
Max
Unit
DCLK pulse width high
DCLK pulse width low
DFS set-up time to DCLK rising edge
DFS hold time from DCLK rising edge
DIN set-up time from DCLK rising edge
DIN hold time from DCLK rising edge
DCLK, DFS, DIN, Rise/Fall time
DCLK Tx Frequency1,2
tDCH
tDCL
tSU:DFS
tHD:DFS
tSU:DIN
tHD:DIN
tR
tF
10 — — ns
10 — — ns
5 — — ns
5 — — ns
5 — — ns
5 — — ns
— — 10 ns
1.0
40.0
MHz
Notes:
1. Guaranteed by characterization.
2. The DCLK frequency may be set below the minimum specification if DIGITAL_INPUT_SAMPLE_RATE is first set to 0
(disable).
DCLK
DFS
tHD:DFS
tR
tSU:DFS
tF
DIN
tSU:DIN
tHD:DIN
Figure 8. Digital Audio Interface Timing Parameters, I2S Mode
Rev. 1.1
11

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