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EN6360QI Datasheet PDF Download - Enpirion

Номер произв EN6360QI
Описание 8A Synchronous Highly Integrated DC-DC PowerSoC
Производители Enpirion
логотип Enpirion логотип 
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EN6360QI Даташит, Описание, Даташиты
EN6360QI
8A Synchronous Highly Integrated DC-DC
PowerSoC
Description
The EN6360QI is a Power System on a Chip
(PowerSoC) DC to DC converter with an integrated
inductor, PWM controller, MOSFETs and
compensation to provide the smallest solution size in
an 8x11x3mm 68 pin QFN module. It offers high
efficiency, excellent line and load regulation over
temperature and up to the full 8A load range. The
EN6360QI is specifically designed to meet the
precise voltage and fast transient requirements of
high-performance, low-power processor, DSP, FPGA,
memory boards and system level applications in
distributed power architecture. The EN6360QI
features switching frequency synchronization with an
external clock or other EN6360QIs for parallel
operation. Other features include precision enable
threshold, pre-bias monotonic start-up, and
programmable soft-start. The device’s advanced
circuit techniques, ultra high switching frequency, and
proprietary integrated inductor technology deliver
high-quality, ultra compact, non-isolated DC-DC
conversion.
The Enpirion integrated inductor solution significantly
helps to reduce noise. The complete power converter
solution enhances productivity by offering greatly
simplified board design, layout and manufacturing
requirements. All Enpirion products are RoHS
compliant and lead-free manufacturing environment
compatible.
Features
High Efficiency (Up to 96%)
Excellent Ripple and EMI Performance
Up to 8A Continuous Operating Current
Input Voltage Range (2.5V to 6.6V)
Frequency Synchronization (Clock or Primary)
2% VOUT Accuracy (Over Line/Load/Temperature)
Optimized Total Solution Size (190mm2)
Precision Enable Threshold for Sequencing
Programmable Soft-Start
Master/Slave Configuration for Parallel Operation
Thermal Shutdown, Over-Current, Short Circuit,
and Under-Voltage Protection
RoHS Compliant, MSL Level 3, 260°C Reflow
Applications
Point of Load Regulation for Low-Power, ASICs
Multi-Core and Communication Processors, DSPs,
FPGAs and Distributed Power Architectures
Blade Servers, RAID Storage and LAN/SAN
Adapter Cards, Wireless Base Stations, Industrial
Automation, Test and Measurement, Embedded
Computing, and Printers
High Efficiency 12V Intermediate Bus Architectures
Beat Frequency/Noise Sensitive Applications
VIN
2x
22 F
1206
PVIN
VOUT
ENABLE
EN6360QI
AVIN
SS VFB
VOUT
2x
F
1206
RA CA
R1
15nF
PGND
PGND
AGND FQADJ
RFQADJ
RB
Figure 1. Simplified Applications Circuit
100
90
80
70
60
50
40
30
20
10
0
0
Efficiency vs. Output Current
CONDITIONS
VIN = 5.0V
VOUT = 3.3V
VOUT = 1.2V
Actual Solution Size
190mm2
123456
OUTPUT CURRENT (A)
7
8
Figure 2. Highest Efficiency in Smallest Solution Size
06489
April 16, 2012
www.enpirion.com
Rev: C
--------------------------------------------

No Preview Available !

EN6360QI Даташит, Описание, Даташиты
EN6360QI
Ordering Information
Part Number
EN6360QI
EN6360QI-E
Package Markings
EN6360QI
EN6360QI
Temp Rating (°C)
-40 to +85
Package Description
68-pin (8mm x 11mm x 3mm) QFN T&R
QFN Evaluation Board
Packing and Marking Information: http://www.enpirion.com/resource-center-packing-and-marking-information.htm
Pin Assignments (Top View)
NC 1
NC 2
NC 3
NC 4
NC 5
NC 6
NC 7
NC 8
NC 9
NC 10
NC 11
NC 12
NC 13
NC 14
KEEP OUT
KEEP OUT
69
PGND
48 S_IN
47 BGND
46 VDDB
45 NC
44 NC
43 PVIN
42 PVIN
41 PVIN
40 PVIN
39 PVIN
38 PVIN
37 PVIN
36 PVIN
35 PVIN
Figure 3: Pin Out Diagram (Top View)
NOTE A: NC pins are not to be electrically connected to each other or to any external signal, ground, or voltage.
However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage.
NOTE B: Shaded area highlights exposed metal below the package that is not to be mechanically or electrically
connected to the PCB. Refer to Figure 11 for details.
NOTE C: White ‘dot’ on top left is pin 1 indicator on top of the device package.
Pin Description
PIN
1-15, 25,
44-45,
59, 64-68
16-24
NAME
NC
VOUT
FUNCTION
NO CONNECT: These pins must be soldered to PCB but not electrically connected to each
other or to any external signal, voltage, or ground. These pins may be connected internally.
Failure to follow this guideline may result in device damage.
Regulated converter output. Connect to the load and place output filter capacitor(s) between
these pins and PGND pins 28 to 31.
©Enpirion 2011 all rights reserved, E&OE
06489
Enpirion Confidential
April 16, 2012
www.enpirion.com, Page 2
Rev: C
--------------------------------------------

No Preview Available !

EN6360QI Даташит, Описание, Даташиты
PIN
26-27,
62-63
28-34
35-43
46
47
48
49
50
51
52
53
54
55
56
57
58
60
61
69
EN6360QI
NAME
NC(SW)
PGND
PVIN
VDDB
BGND
S_IN
S_OUT
POK
ENABLE
AVIN
AGND
M/S
VFB
EAOUT
SS
VSENSE
FQADJ
EN_PB
PGND
FUNCTION
NO CONNECT: These pins are internally connected to the common switching node of the
internal MOSFETs. They must be soldered to PCB but not be electrically connected to any
external signal, ground, or voltage. Failure to follow this guideline may result in device damage.
Input and output power ground. Connect these pins to the ground electrode of the input and
output filter capacitors. Refer to VOUT, PVIN descriptions and Layout Recommendation for
more details.
Input power supply. Connect to input power supply and place input filter capacitor(s) between
these pins and PGND pins 32 to 34.
Internal regulated voltage used for the internal control circuitry. Decouple with an optional
0.1µF capacitor to BGND for improved efficiency. This pin may be left floating if board space is
limited.
Ground for VDDB. Refer to pin 46 description.
Digital input. A high level on the M/S pin will make this EN6360QI a Slave and the S_IN will
accept the S_OUT signal from another EN6360QI for parallel operation. A low level on the M/S
pin will make this device a Master and the switching frequency will be phase locked to an
external clock. Leave this pin floating if it is not used.
Digital output. A low level on the M/S pin will make this EN6360QI a Master and the internal
switching PWM signal is output on this pin. This output signal is connected to the S_IN pin of
another EN6360QI device for parallel operation. Leave this pin floating if it is not used.
POK is a logic level high when VOUT is within -10% to +20% of the programmed output
voltage (0.9VOUT_NOM VOUT 1.2VOUT_NOM). This pin has an internal pull-up resistor to AVIN
with a nominal value of 120k.
Device enable pin. A high level or floating this pin enables the device while a low level disables
the device. A voltage ramp from another power converter may be applied for precision enable.
Refer to Power Up Sequencing
Analog input voltage for the control circuits. Connect this pin to the input power supply (PVIN)
at a quiet point. Can also be connected to an auxiliary supply within a voltage range that is
sequencing.
The quiet ground for the control circuits. Connect to the ground plane with a via right next to the
pin.
Ternary (three states) input pin. Floating this pin disables parallel operation. A low level
configures the device as Master and a high level configures the device as a Slave. A REXT
resistor is recommended to pulling M/S high. Refer to Ternary Pin description in the Functional
Description section for REXT values. Also refer to S_IN and S_OUT pin descriptions.
This is the external feedback input pin. A resistor divider connects from the output to AGND.
The mid-point of the resistor divider is connected to VFB. A feed-forward capacitor (CA) and
resistor (R1) are required parallel to the upper feedback resistor (RA). The output voltage
regulation is based on the VFB node voltage equal to 0.600V. For Slave devices, leave VFB
floating.
Error amplifier output. Allows for customization of the control loop. May be left floating.
A soft-start capacitor is connected between this pin and AGND. The value of the capacitor
controls the soft-start interval. Refer to Soft-Start in the Functional Description for more details.
This pin senses output voltage when the device is in pre-bias (or back-feed) mode. Connect
VSENSE to VOUT when EN_PB is high or floating. Leave floating when EN_PB is low.
Frequency adjust pin. This pin must have a resistor to AGND which sets the free running
frequency of the internal oscillator.
Enable pre-bias input. When this pin is pulled high, the device will support monotonic start-up
under a pre-biased load. VSENSE must be tied to VOUT for EN_PB to function. This pin is
pulled high internally. Enable pre-bias feature is not available for parallel operations.
Not a perimeter pin. Device thermal pad to be connected to the system GND plane for heat-
sinking purposes. Refer to Layout Recommendation section.
©Enpirion 2011 all rights reserved, E&OE
06489
Enpirion Confidential
April 16, 2012
www.enpirion.com, Page 3
Rev: C
--------------------------------------------





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