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ADP5135 PDF даташит

Спецификация ADP5135 изготовлена ​​​​«Analog Devices» и имеет функцию, называемую «Triple 1800 mA Buck Regulators».

Детали детали

Номер произв ADP5135
Описание Triple 1800 mA Buck Regulators
Производители Analog Devices
логотип Analog Devices логотип 

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ADP5135 Даташит, Описание, Даташиты
Triple 1800 mA Buck Regulators
With Precision Enables and Power Good Outputs
Preliminary Data Sheet
ADP5135
FEATURES
Main input voltage range: 3.0 V to 5.5 V
Three 1800 mA buck regulators
24-lead, 4 mm × 4 mm LFCSP package
Regulator accuracy: ±1.8%
Factory programmable or external adjustable VOUTx
Precision Enables for easier power sequencing
Power Good Pins for monitoring of each regulator
3 MHz buck operation with forced PWM and auto PWM/PSM
modes
BUCK1/BUCK2/BUCK3: output voltage range from 0.8 V to
3.8 V
APPLICATIONS
Power for processors, ASICS, FPGAs, and RF chipsets
Portable instrumentation and medical devices
Space constrained devices
GENERAL DESCRIPTION
Table 1. Family Models
Model Channels
Max Current Package
ADP5023 2 Bucks,1 LDO
ADP5024 2 Bucks,1 LDO
800mA, 300mA
1.2A, 300mA
ADP5034 2 Bucks,2 LDOs
1.2A, 300mA
ADP5037 2 Bucks,2 LDOs
800mA, 300mA
ADP5033
2 Bucks,2 LDOs with 2
EN pins
800mA, 300mA
ADP5040 1 Buck, 2 LDOs
1.2A, 300mA
ADP5041
1 Buck, 2 LDOs w/
Supevisory,
Watchdog, Manual
Reset
1.2A, 300mA
LFCSP (CP-24-10)
LFCSP (CP-24-10)
LFCSP (CP-24-10),
TSSOP (RE-28-1)
LFCSP (CP-24-10)
WLCSP (CB-16-8)
LFCSP (CP-20-10)
LFCSP (CP-20-10)
The ADP5135 combines three high performance buck
regulators. It is available in a 24-lead 4 mm × 4 mm LFCSP.
The high switching frequency of the buck regulators enables tiny
multilayer external components and minimizes the board space.
When the MODE pin is set to high, the buck regulators operate in
forced PWM mode. When the MODE pin is set to low, the buck
regulators operate in PWM mode only when the load is above a
predefined threshold. When the load current falls below this
predefined threshold, the regulator operates in power save
mode (PSM), improving the light load efficiency.
ADP5133 2 Bucks with 2 EN pins 800mA
WLFCSP (CB-16-8)
ADP5134
2 Bucks,2 LDOs w/ PE
and PG
1.2A, 300mA
LFCSP (CP-24-10)
Buck1 and Buck2 operate in sync and Buck3 operates out of
phase to reduce the input capacitor requirement.
Regulators in the ADP5135 are activated through dedicated
enable pins. The default output voltages can be externally set in
the adjustable version, or factory programmable to a wide range
of preset values in the fixed voltage version.
TYPICAL APPLICATION CIRCUIT
Figure 1.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights ofthird parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2014 Analog Devices, Inc. All rights reserved.









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ADP5135 Даташит, Описание, Даташиты
ADP5135
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Typical Application Circuit ............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
General Specifications ................................................................. 3
BUCK1, BUCK2 and BUCK3 Specifications............................ 4
Input and Output Capacitor, Recommended Specifications.. 4
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Preliminary Data Sheet
Rev. PrA | Page 2 of 25









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ADP5135 Даташит, Описание, Даташиты
Preliminary Data Sheet
ADP5135
SPECIFICATIONS
GENERAL SPECIFICATIONS
VAVIN = VIN1 = VIN2 = VIN3 = 3.0 V to 5.5 V; TJ = −40°C to +125°C for minimum/maximum speci cations, and TA = 25°C for typical
specifications, unless otherwise noted.
Table 2.
Parameter
Symbol
Test Conditions/Comments
Min Typ Max Unit
INPUT VOLTAGE RANGE
THERMAL SHUTDOWN
Threshold
Hysteresis
START-UP TIME1
BUCK1
BUCK2
BUCK3
START-UP TIME, BUCK3 first
BUCK3
BUCK1
BUCK2
SHUTDOWN CONTROL
Level High
Level Low
VAVIN, VIN1,
VIN2, VIN3
TSSD
TSSD-HYS
tSTART1
tSTART2
tSTART3
tSTART4
tSTART5
tSTART6
VIH_EN
VIL_EN
3.0 5.5 V
TJ rising
All ENx pins below VIL_EN level to achive ISHUTDOWN
TJ = −40°C to +85°C
0.9
150 °C
20 °C
650 µs
750 µs
750 µs
750 µs
300 µs
400 µs
V
0.35 V
PRECISION ENABLE PINS
Analog Activation Threshold
Hysteresis (Regulator Deactivation)
Input Leakage Current
POWER GOOD PINS
Power Good Falling Threshold
Power Good Rising Threshold
Power Good Delay
Power Good Leakage Current
Power Good Output Voltage Low
MODE PIN
Level High
Level Low
INPUT CURRENT
VENR
VENH
VI-LEAKAGE
VPGLOW
VPGHYS
tPGDLY
IPGIQ
VPGOL
VIH_MOD
VIL_MOD
Regulator(s) activation/deactivation thresholds
Device out of shutdown (VENx > VIH_EN )
0.94 0.97 1
80
0.05 1
Monitors Vout falling out of regulation
85
91 94 97
20
VPG = VIN
Load current = 1mA
1
0.1 0.2
No load, no buck switching
1.1
0.4
V
mV
uA
%Vout
%Vout
us
uA
V
V
V
All Channels Enabled
All Channels Disabled
VIN1 UNDERVOLTAGE LOCKOUT
Mid UVLO Input Voltage Rising
Mid UVLO Input Voltage Falling
ISTBY-NOSW
ISHUTDOWN
TJ = −40°C to +85°C
UVLOVIN1RISE
UVLOVIN1FALL
85 108 µA
0.3 1
µA
2.95 V
2.5 V
1 Start-up time is defined as the time from EN1 = EN2 = EN3 from 0 V to VAVIN to VOUT1, VOUT2, and VOUT3 reaching 90% of their nominal level. Start-up times are
shorter for individual channels if another channel is already enabled. See the Typical Performance Characteristics section for more information.
Rev. PrA | Page 3 of 25










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