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PDF AD7981 Data sheet ( Hoja de datos )
| Número de pieza | AD7981 | |
| Descripción | 600 kSPS PulSAR ADC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
FEATURES
Extreme high temperature operation
Specified temperature range: −55°C to +175°C
High performance
16-bit resolution with no missing codes
600 kSPS throughput with no latency/pipeline delay
SNR: 91 dB typical at 1 kHz input frequency
THD: −102 dB typical at 1 kHz input frequency
INL: ±2.0 LSB maximum, DNL: ±0.9 LSB maximum
Low power dissipation
2.25 mW typical at 600 kSPS (VDD only)
4.65 mW typical at 600 kSPS (total)
70 µW typical at 10 kSPS
Small footprint
10-lead, 3 mm × 5 mm, monometallic wire bonding MSOP
Pseudo differential analog input range
0 V to VREF with VREF between 2.4 V and 5.1 V
Easy to use
Single-supply 2.5 V operation with 1.8 V/2.5 V/3 V/5 V logic
interface
SPI-/QSPI-/MICROWIRE-/DSP-compatible digital interface
Daisy-chain multiple ADCs and busy indicator
APPLICATIONS
Downhole drilling and instrumentation
Avionics
Heavy industrial
High temperature environments
GENERAL DESCRIPTION
The AD79811 is a 16-bit, successive approximation, analog-to-
digital converter (ADC) designed for high temperature operation.
The AD7981 is capable of sample rates up to 600 kSPS while
maintaining low power consumption from a single power supply,
VDD. It is a fast throughput, high accuracy, high temperature,
successive approximation register (SAR) ADC and packaged in
a small form factor with a versatile serial port interface (SPI).
On the CNV rising edge, the AD7981 samples an analog input,
IN+, between 0 V and REF with respect to a ground sense, IN−.
The reference voltage, REF, is applied externally and can be set
independent of the supply voltage, VDD. The device power
scales linearly with throughput.
The SPI-compatible serial interface also features the ability,
using the SDI input, to daisy-chain several ADCs on a single,
1 Protected by U.S. Patent 6,703,961.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
High Temperature, 16-Bit,
600 kSPS PulSAR® ADC
AD7981
TYPICAL APPLICATION CIRCUIT
2.5V to 5.0V 2.5V
0V TO VREF
REF VDD VIO
IN+ SDI
AD7981 SCK
IN– SDO
GND
CNV
1.8V TO 5.0V
3- OR 4-WIRE INTERFACE
(SPI, DAISY CHAIN, CS)
Figure 1.
3-wire bus and provides an optional busy indicator. It is compatible
with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate supply VIO.
For space constrained applications, the AD7981 is available in a
10-lead mini small outline package (MSOP) with operation
specified from −55°C to +175°C. This package is designed for
robustness at extreme temperatures, including monometallic
wire bonding, and is qualified for up to 1000 hours of operation
at the maximum temperature rating.
The AD7981 is a member of a growing series of high temperature
qualified products offered by Analog Devices, Inc. For a complete
selection of available high temperature products, see the high
temperature product list and qualification data available at
www.analog.com/hightemp.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
AD7981
TIMING SPECIFICATIONS
TA = −55°C to +175°C, VDD = 2.375 V to 2.625 V, VIO = 3.3 V to 5.5 V, unless otherwise stated. See Figure 2 and Figure 3 for load conditions.
Table 3.
Parameter
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
CNV Pulse Width (CS Mode)
SCK Period (CS Mode)
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK Period (Chain Mode)
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
VIO Above 3 V
VIO Above 2.3 V
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (Chain Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with Busy Indicator)
Symbol Min
Typ Max Unit
tCONV
625
900 ns
tACQ 290
ns
tCYC 1667
ns
tCNVH
10
ns
tSCK
10.5 ns
12 ns
13 ns
15 ns
tSCK
11.5 ns
13 ns
14 ns
16 ns
tSCKL
tSCKH
4.5
4.5
ns
ns
tHSDO
3
ns
tDSDO
9.5 ns
11 ns
12 ns
14 ns
tEN
10 ns
15 ns
tDIS 20 ns
tSSDICNV
tHSDICNV
5
2
ns
ns
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
0
5
5
2
ns
ns
ns
ns
tHSDISCK
3
ns
tDSDOSDI
15 ns
500µA IOL
TO SDO
CL
20pF
1.4V
500µA IOH
Figure 2. Load Circuit for Digital Interface Timing
X% VIO1
tDELAY
VIH2
VIL2
Y% VIO1
tDELAY
VIH2
VIL2
1FOR VIO ≤ 3.0V, X = 90 AND Y = 10; FOR VIO > 3.0V, X = 70 AND Y = 30.
2MINIMUM VIH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS
SPECIFICATIONS IN TABLE 2.
Figure 3. Voltage Levels for Timing
Rev. 0 | Page 5 of 25
5 Page 
Data Sheet
200
IVDD
180
IVIO
IVDD + IVIO
160
140
120
100
80
60
40
20
0
–60 –40 –20 0 20 40 60 80 100 120 140 160 180 200 220
TEMPERATURE (°C)
Figure 23. Power-Down Current vs. Temperature
AD7981
Rev. 0 | Page 11 of 25
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet AD7981.PDF ] | |
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