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Спецификация AN10935 изготовлена «NXP Semiconductors» и имеет функцию, называемую «Using SDR/DDR SDRAM memories». |
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Детали детали
Номер произв | AN10935 |
Описание | Using SDR/DDR SDRAM memories |
Производители | NXP Semiconductors |
логотип |
47 Pages
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AN10935
Using SDR/DDR SDRAM memories with LPC32xx
Rev. 2 — 11 October 2010
Application note
Document information
Info Content
Keywords
LPC32x0, LPC32xx, LPC3220, LPC3230, LPC3240, LPC3250, SDR,
SDRAM, DDR
Abstract
This application note covers hardware related issues for interfacing SDR
or DDR SDRAMs to the LPC32xx family microcontroller.
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NXP Semiconductors
Revision history
Rev Date
2 20101011
1 20100603
Description
• Add Section 2.4.
• Updated Table 6.
• Updated Table 7.
Initial version
AN10935
Using SDR/DDR SDRAM memories with LPC32xx
Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
AN10935
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 11 October 2010
© NXP B.V. 2010. All rights reserved.
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NXP Semiconductors
AN10935
Using SDR/DDR SDRAM memories with LPC32xx
1. Introduction
NXP’s LPC32x0 32-bit microcontroller was designed for embedded applications requiring
high performance and low power consumption. The LPC32x0 is based on the
ARM926EJ-S CPU core with a Vector Floating Point co-processor, and a large set of
standard peripherals. The basic ARM926EJ-S CPU Core implementation uses Harvard
architecture with a 5-stage pipeline, and has one 32 kB instruction cache and one 32 kB
data cache. The ARM926EJ-S core also has an integral Memory Management Unit
(MMU) to provide the virtual memory capabilities required to support the multi-
programming demands of modern operating systems. The LPC32x0 comes with internal
static memory ranging between 128 kB to 256 kB. While this is enough memory for some
embedded applications, many applications require larger amounts of memory. The
LPC32x0 has an integrated External Memory Controller (EMC) for interfacing to external
memories.
The LPC32x0 EMC is an ARM PrimeCell MultiPort Memory Controller peripheral offering
support for asynchronous static memory devices such as RAM, ROM and Flash, as well
as dynamic memories such as Single Data Rate (SDR) and Double Data Rate (DDR)
SDRAM. For external memory of 2 MB or larger the most practical memories to use
today are SDR or DDR SDRAM.
This application note will focus on connectivity, initialization and board layout guidelines
when using SDR and DDR memories with the LPC32x0.
2. External memory controller
The LPC32x0 uses an expanded AMBA high-performance bus (AHB) architecture known
as Multi-layer AHB. A Multi-layer AHB replaces the request/grant and arbitration
mechanism used in a simple AHB with an interconnect matrix that moves arbitration out
toward the slave devices. Within the interconnect matrix each slave port has its own
arbitration block. Thus, if a CPU and a DMA controller want access to the same memory,
the interconnect matrix arbitrates between the two when granting access to the memory.
The LPC32x0 has seven AHB masters: the CPU data bus, CPU instruction bus, two
general purpose DMA masters, Ethernet controller, USB controller, and LCD controller.
The AHB masters access external memory through the EMC on one of three AHB slave
ports. A block diagram of how the LPC32x0 bus masters connect to the EMC through the
Multi-layer AHB interconnect matrix is shown in Fig 1. The EMC translates AHB master
requests on the slave AHB ports for access to external memory into commands and data
transactions that follow the selected memory protocol.
AN10935
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 11 October 2010
© NXP B.V. 2010. All rights reserved.
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