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PDF ADP5051 Data sheet ( Hoja de datos )
| Número de pieza | ADP5051 | |
| Descripción | Integrated Power Solution | |
| Fabricantes | Analog Devices | |
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Data Sheet
Integrated Power Solution with Quad Buck
Regulators, Supervisory Circuit, and I2C Interface
ADP5051
FEATURES
Wide input voltage range: 4.5 V to 15.0 V
±1.5% output accuracy over full temperature range
250 kHz to 1.4 MHz adjustable switching frequency
Adjustable/fixed output options via factory fuse or I2C interface
I2C interface with interrupt on fault conditions
Power regulation
Channel 1 and Channel 2: programmable 1.2 A/2.5 A/4 A
sync buck regulators with low-side FET driver
Channel 3 and Channel 4: 1.2 A sync buck regulators
Single 8 A output (Channel 1 and Channel 2 in parallel)
Dynamic voltage scaling (DVS) for Channel 1 and Channel 4
Precision enable with 0.8 V accurate threshold
Active output discharge switch
Programmable phase shift in 90° steps
Individual channel FPWM/PSM selection
Frequency synchronization input or output
Optional latch-off protection on OVP/OCP failure
Power-good flag on selected channels
Low input voltage detection
Open-drain processor reset with external adjustable threshold
monitoring
Watchdog refresh input
Manual reset input
Overheat detection on junction temperature
UVLO, OCP, and TSD protection
APPLICATIONS
Small cell base stations
FPGA and processor applications
Security and surveillance
Medical applications
GENERAL DESCRIPTION
The ADP5051 combines four high performance buck regulators
and a supervisory circuit with a voltage monitor, a watchdog
function, and a manual reset in a 48-lead LFCSP package that
meets demanding performance and board space requirements.
The device enables direct connection to high input voltages up to
15.0 V with no preregulators.
Channel 1 and Channel 2 integrate high-side power MOSFET and
low-side MOSFET drivers. In low-side power devices, use external
NFETs to achieve an efficiency optimized solution and deliver a
programmable output current of 1.2 A, 2.5 A, or 4 A.
TYPICAL APPLICATION CIRCUIT
C1
4.5V TO 15V
VREG
VDD
C0
PVIN1
C2
COMP1
EN1
SS12
C5 PVIN2
COMP2
EN2
ADP5051
INT VREG
100mA
OSCILLATOR
CHANNEL 1
BUCK
(4A)
VREG
CHANNEL 2
BUCK
(4A)
VREG
SYNC/MODE
RT
FB1
BST1
SW1 C3
DL1 Q1
PGND RILIM1
DL2 RILIM2
SW2
Q2
BST2
FB2
C6
L1
L2
VOUT1
C4
VOUT2
C7
PVIN3
C8
COMP3
EN3
SS34
PVIN4
C11
COMP4
EN4
CHANNEL 3
BUCK
(1.2A)
CHANNEL 4
BUCK
(1.2A)
BST3
SW3
C9
FB3
PGND3
BST4
C12
SW4
FB4
PGND4
L3 VOUT3
C10
L4
VREG
VOUT4
C13
WDI
WATCHDOG
MR AND
RESET
RSTO
VTH
VOUTx
VDDIO
SCL
SDA
I2C ALERT
PWRGD
INT
EXPOSED PAD
Figure 1.
Combining Channel 1 and Channel 2 in a parallel configuration
provides a single output with up to 8 A of current. Channel 3 and
Channel 4 integrate both high-side and low-side MOSFETs to
deliver an output current of 1.2 A.
The ADP5051 supervisory circuits monitor the voltage level.
The watchdog timer generates a reset when the WDI pin does
not toggle within a preset timeout period. Select manual reset
functionality via the processor reset mode or system power on/off
switch mode.
The optional I2C interface offers flexible configurations, including
adjustable and fixed output voltage, junction temperature overheat
warning, low input voltage detection, and dynamic voltage scaling.
Table 1. Family Models
Model
Channels
I2C Package
ADP5050 Four bucks, one LDO
Yes 48-Lead LFCSP
ADP5051 Four bucks, supervisory Yes 48-Lead LFCSP
ADP5052 Four bucks, one LDO
No 48-Lead LFCSP
ADP5053 Four bucks, supervisory No 48-Lead LFCSP
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
ADP5051
SPECIFICATIONS
VIN = 12 V, VVREG = 5.1 V, TJ = −40°C to +125°C for minimum and maximum specifications, and TA = 25°C for typical specifications,
unless otherwise noted.
Table 2.
Parameter
INPUT SUPPLY VOLTAGE RANGE
QUIESCENT CURRENT
Operating Quiescent Current
UNDERVOLTAGE LOCKOUT
Threshold
Rising
Falling
Hysteresis
OSCILLATOR CIRCUIT
Switching Frequency
Range
SYNC Input
Input Clock Range
Input Clock Pulse Width
Minimum On Time
Minimum Off Time
Input Clock High Voltage
Input Clock Low Voltage
SYNC Output
Clock Frequency
Positive Pulse Duty Cycle
Rise or Fall Time
High Level Voltage
PRECISION ENABLING
High Level Threshold
Low Level Threshold
Pull-Down Resistor
POWER GOOD
Internal Power Good
Rising Threshold
Hysteresis
Falling Delay
Rising Delay for PWRGD Pin
Leakage Current for PWRGD Pin
Output Low Voltage for PWRGD Pin
LOGIC INPUTS (SCL AND SDA PINS)
Threshold Level
High
Low
LOGIC OUTPUTS
Low Level Output Voltage
SDA Pin
INT Pin
Symbol
VIN
Min
4.5
IQ
ISHDN
UVLO
VUVLO-RISING
VUVLO-FALLING
VHYS
3.6
fSW 700
250
fSYNC
250
tSYNC_MIN_ON
tSYNC_MIN_OFF
VH (SYNC)
VL (SYNC)
100
100
1.3
fCLK
tCLK_PULSE_DUTY
tCLK_RISE_FALL
VH (SYNC_OUT)
VTH_H (EN)
VTH_L (EN)
RPULL-DOWN (EN)
0.688
Typ Max
15.0
4.8 6.35
25 65
4.2 4.36
3.78
0.42
740 780
1400
1400
0.4
fSW
50
10
VVREG
0.806
0.725
1.0
0.832
Unit Test Conditions/Comments
V PVIN1, PVIN2, PVIN3, PVIN4 pins
PVIN1, PVIN2, PVIN3, PVIN4 pins
mA No switching, all ENx pins high
µA All ENx pins low
PVIN1, PVIN2, PVIN3, PVIN4 pins
V
V
V
kHz RT = 25.5 kΩ
kHz
kHz
ns
ns
V
V
kHz
%
ns
V
EN1, EN2, EN3, EN4 pins
V
V
MΩ
VPWRGD (RISE)
VPWRGD (HYS)
tPWRGD_FALL
tPWRGD_PIN_RISE
IPWRGD_LEAKAGE
VPWRGD_LOW
86.3
90.5 95
3.3
50
1
0.1 1
50 100
%
%
µs
ms
µA
mV IPWRGD = 1 mA
VDDIO = 3.3 V
VLOGIC_HIGH
VLOGIC_LOW
0.7 × VDDIO
V
0.3 × VDDIO V
VSDA_LOW
VINT_LOW
0.4 V VDDIO = 3.3 V, ISDA = 3 mA
0.4 V IINT = 3 mA
Rev. 0 | Page 5 of 60
5 Page 
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADP5051
BST3 1
PGND3 2
SW3 3
PVIN3 4
WDI 5
VTH 6
MR 7
RSTO 8
PVIN4 9
SW4 10
PGND4 11
BST4 12
ADP5051
TOP VIEW
(Not to Scale)
36 PVIN1
35 PVIN1
34 SW1
33 SW1
32 BST1
31 DL1
30 PGND
29 DL2
28 BST2
27 SW2
26 SW2
25 PVIN2
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED AND
SOLDERED TO AN EXTERNAL GROUND PLANE.
Figure 4. Pin Configuration
Table 8. Pin Function Descriptions
Pin No. Mnemonic Description
1 BST3
High-Side FET Driver Power Supply for Channel 3.
2
PGND3
Power Ground for Channel 3.
3 SW3
Switching Node Output for Channel 3.
4 PVIN3 Power Input for Channel 3. Connect a bypass capacitor between this pin and ground.
5 WDI
Watchdog Refresh Input from Processor.
6 VTH
Monitoring Voltage Threshold Programming.
7 MR
Manual Reset Input, Active Low.
8 RSTO
Open-Drain Reset Output, Active Low.
9 PVIN4 Power Input for Channel 4. Connect a bypass capacitor between this pin and ground.
10 SW4
Switching Node Output for Channel 4.
11 PGND4 Power Ground for Channel 4.
12 BST4
High-Side FET Driver Power Supply for Channel 4.
13 INT
Interrupt Output on Fault Condition. Open-drain output port.
14 EN4
Enable Input for Channel 4. Use an external resistor divider to set the turn-on threshold.
15 COMP4 Error Amplifier Output for Channel 4. Connect an RC network from this pin to ground.
16 FB4
Feedback Sensing Input for Channel 4.
17 VDDIO Power Supply for the I2C Interface.
18 SDA
Data Input/Output for the I2C Interface. Open-drain I/O port.
19 SCL
Clock Input for the I2C Interface.
20
PWRGD
Power-Good Signal Output. This open-drain output is the power-good signal for the selected channels. This pin
can be programmed by the factory to set the I2C address of the device; the I2C address setting function replaces
the power-good function on this pin. For more information, see the I2C Addresses section.
21 FB2
Feedback Sensing Input for Channel 2.
22 COMP2 Error Amplifier Output for Channel 2. Connect an RC network from this pin to ground.
23 EN2
Enable Input for Channel 2. Use an external resistor divider to set the turn-on threshold.
24, 25 PVIN2
Power Input for Channel 2. Connect a bypass capacitor between this pin and ground.
26, 27 SW2
Switching Node Output for Channel 2.
28 BST2
High-Side FET Driver Power Supply for Channel 2.
Rev. 0 | Page 11 of 60
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADP5051.PDF ] | |
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