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PDF MDT10F630 Data sheet ( Hoja de datos )
| Número de pieza | MDT10F630 | |
| Descripción | 8-bit Micro-controller | |
| Fabricantes | Micon Design Technology | |
| Logotipo |  |
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1. General Description
This 8-bit Micro-controller uses a fully static
CMOS technology to achieve high speed, small
size, low power and high noise immunity.
On chip memory includes 1 K words of Flash
ROM, and 128 bytes of EEPROM, and 64 bytes
of static RAM.
2. Features
Fully CMOS static design
8-bit data bus
On chip flash ROM size :
MDT10F630 -- 1 K words
Internal RAM size :
MDT10F630 -- 64 bytes
(64 general purpose registers)
128 bytes of EEPROM
37 single word instructions
14-bit instructions
8-level stacks
Operating voltage : 2.3V ~ 5.5 V
Watchdog timer with on-chip RC oscillator
Interrupt capability
Timer0 : 8-bit timer with 3-bit prescaler
Timer1 : 16-bit timer with 2-bit prescaler
One analog comparator module
Sleep mode for power saving
PA with port change wake-up interrupt
Power-on Reset
12 I/O pins with their own independent
direction control
3. Applications
The application areas of this MDT10F630 range
from appliance motor control and high speed
MDT10F630
automotive to low power remote
transmitters/receivers, pointing devices, and
telecommunications processors, such as Remote
controller, small instruments, chargers, toy,
automobile and PC peripheral … etc.
4. Pin Assignment
MDT10F630P11 (DIP)
MDT10F630S11 (SOP)
Vdd
OSC1/PA5
OSC2/PA4
PA3
PC5
PC4
PC3
1
2
3
4
5
6
7
14 Vss
13 PA0/CIN+
12 PA1/CIN-
11 PA2/INT
10 PC0
9 PC1
8 PC2
MDT10F630P13 (DIP)
MDT10F630S13 (SOP)
Vdd
OSC1/PA5
OSC2/PA4
/MCLR
PC5
PC4
PC3
1
2
3
4
5
6
7
14 Vss
13 PA0/CIN+
12 PA1/CIN-
11 PA2/INT
10 PC0
9 PC1
8 PC2
This specification is subject to be changed without notice. Please visit our web site for the most updated information.
http://www.mdtic.com.tw
P.1
2008/4 Ver. 1.0
1 page  
MDT10F630
(1). 00H or 80H : IAR ( Indirect Address Register)
Use contents of MSR to address data memory (not a physical register)
(2). 01H : RTCC (Timer0 Counter)
8-bit real time clock/counter
(3). 02H or 82H : PCL (Program Counter Low Byte)
Low order 8 bits of the Program Counter (PC)
(4). 03H or 83H : STATUS (Status register)
Bit Symbol
Function
0
1
2
3
4
5
6—7
C
HC
Z
/PF
/TF
page
——
Carry bit
Half Carry bit
Zero bit
Power loss Flag bit
WDT time-out Flag bit
Register page select bit :
0 : 00H --- 7FH
1 : 80H --- FFH
General purpose bit
(5). 04H or 84H : MSR (Memory Select Register)
Memory Bank Select Register :
0 : 00~7F (Bank0)
1 : 80~FF (Bank1)
MSR
Bit 7
Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(6). 05H : Port A data output register
Indirect Addressing Mode
Port A
Bit 7
-
Bit 6
-
Bit 5
PA5
Bit 7-6 : Unimplemented
Bit 5-0 : PA5~PA0, I/O Register
(7). 06H : Unimplemented Register.
Bit 4
PA4
Bit 3
PA3
Bit 2
PA2
Bit 1
PA1
Bit 0
PA0
This specification is subject to be changed without notice. Please visit our web site for the most updated information.
http://www.mdtic.com.tw
P.5
2008/4 Ver. 1.0
5 Page 
MDT10F630
(32). 96H : Port A interrupt-on-change control register.
PAINTR
Bit 7
-
Bit 6
-
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PINTA5 PINTA4 PINTA3 PINTA2 PINTA1 PINTA0
Bit 5-0 : Port A Interrupt-On-Change Control Bits
0 = Interrupt-on-change disable
1 = Interrupt-on-change enable
(33).
97 ~ 98H : Unimplemented register.
(34).
99H : Voltage reference control register.
VRSTA
Bit 7
CVREN
Bit 6
-
Bit 5
CVRRS
Bit 4
-
Bit 3
CVR3
Bit 2
CVR2
Bit 1
CVR1
Bit 0
CVR0
(35).
Bit 7 : Comparator Voltage Reference Enable Bit
0 = Comparator voltage reference disable
1 = Comparator voltage reference enable
Bit 5 : Comparator Voltage Reference Range Select Bit
0 = High range ; CVref = Vdd/4 + (CVR3:CVR0/32)*Vdd
1 = Low range ; CVref = (CVR3:CVR0/24)*Vdd
Bit 3-0 : Comparator Voltage Reference Value Selection
When CVRRS = 0, CVref = Vdd/4 + (CVR3:CVR0/32)*Vdd
When CVRRS = 1, CVref = (CVR3:CVR0/24)*Vdd
9AH : EEPROM data register.
EEDATA
Bit 7
EED7
Bit 6
EED6
Bit 5
EED5
Bit 4
EED4
Bit 3
EED3
Bit 2
EED2
Bit 1
EED1
Bit 0
EED0
(36).
9BH : EEPROM address register.
EEADR
Bit 7
-
Bit 6
EEAD6
Bit 5
EEAD5
Bit 4
EEAD4
Bit 3
EEAD3
Bit 2
EEAD2
Bit 1
EEAD1
Bit 0
EEAD0
(37).
9CH : EEPROM control register 1.
EECON1
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
Bit 2
WRERR WREN
Bit 1
WR
Bit 0
RD
Bit 7~4 is unimplemented : Read as “0”
WRERR : EEPROM Write Error Flag Bit.
0 = The EEPROM write operation completed
1 = The EEPROM write operation is prematurely terminated
(any MCLR reset or any WDT reset during normal operation)
This specification is subject to be changed without notice. Please visit our web site for the most updated information.
http://www.mdtic.com.tw
P.11
2008/4 Ver. 1.0
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet MDT10F630.PDF ] | |
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