BUK99E3R2-40B PDF даташит
Спецификация BUK99E3R2-40B изготовлена «NXP Semiconductors» и имеет функцию, называемую «TrenchMOS logic level FET». |
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Детали детали
Номер произв | BUK99E3R2-40B |
Описание | TrenchMOS logic level FET |
Производители | NXP Semiconductors |
логотип |
16 Pages
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BUK95/96/9E3R2-40B
TrenchMOS™ logic level FET
Rev. 04 — 14 November 2003
Product data
1. Product profile
1.1 Description
N-channel enhancement mode field-effect power transistor in a plastic package using
Philips High-Performance Automotive TrenchMOS™ technology.
1.2 Features
s Very low on-state resistance
s 175 °C rated
s Q101 compliant
s Logic level compatible.
1.3 Applications
s Automotive systems
s Motors, lamps and solenoids
s 12 V loads
s General purpose power switching.
1.4 Quick reference data
s EDS(AL)S ≤ 1.2 J
s ID ≤ 100 A
s RDSon = 2.7 mΩ (typ)
s Ptot ≤ 300 W.
2. Pinning information
Table 1: Pinning - SOT78, SOT404, and SOT226 simplified outlines and symbol
Pin Description
Simplified outline
1 gate (g)
2 drain (d)
[1] mb
mb
3 source (s)
mb mounting base,
connected to
drain (d)
mb
Symbol
d
g
MBB076
s
MBK106
123
SOT78 (TO-220AB)
2
1 3 MBK116
123
MBK112
SOT404 (D2-PAK)
SOT226 (I2-PAK)
[1] It is not possible to make connection to pin 2 of the SOT404 package.
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Philips Semiconductors
BUK95/96/9E3R2-40B
TrenchMOS™ logic level FET
3. Ordering information
Table 2: Ordering information
Type number
Package
Name
Description
Version
BUK953R2-40B
TO-220AB Plastic single-ended package; heatsink mounted; 1 mounting hole; 3-lead SOT78
TO-220AB
BUK963R2-40B
D2-PAK
Plastic single-ended surface mounted package (Philips version of D2-PAK); SOT404
3 leads (one lead cropped)
BUK9E3R2-40B I2-PAK
Plastic single-ended package (Philips version of I2-PAK); low-profile 3 lead SOT226
TO-220AB
4. Limiting values
Table 3: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
VDS
VDGR
VGS
ID
drain-source voltage (DC)
drain-gate voltage (DC)
gate-source voltage (DC)
drain current (DC)
RGS = 20 kΩ
Tmb = 25 °C; VGS = 5 V;
Figure 2 and 3
IDM peak drain current
Ptot total power dissipation
Tstg storage temperature
Tj junction temperature
Source-drain diode
IDR reverse drain current (DC)
Tmb = 100 °C; VGS = 5 V; Figure 2
Tmb = 25 °C; pulsed; tp ≤ 10 µs;
Figure 3
Tmb = 25 °C; Figure 1
Tmb = 25 °C
IDRM
reverse drain current
Avalanche ruggedness
EDS(AL)S non-repetitive drain-source avalanche
energy
Tmb = 25 °C; pulsed; tp ≤ 10 µs
unclamped inductive load; ID = 100 A;
VDS ≤ 40 V; VGS = 5 V; RGS = 50 Ω;
starting Tmb = 25 °C
Min
-
-
-
[1] -
[2] -
[2] -
-
-
−55
−55
[1] -
[2] -
-
-
[1] Current is limited by power dissipation chip rating.
[2] All individual parts of device must be ≤ 175 °C to achieve maximum current rating.
Max Unit
40 V
40 V
±15 V
222 A
100 A
100 A
888 A
300
+175
+175
W
°C
°C
222 A
100 A
888 A
1.2 J
9397 750 12049
Product data
Rev. 04 — 14 November 2003
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
2 of 16
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Philips Semiconductors
BUK95/96/9E3R2-40B
TrenchMOS™ logic level FET
120
Pder
(%)
80
03na19
40
0
0 50 100 150 200
Tmb (°C)
Pder = P-------P----t--o---t------- × 100%
t o t ( 25 °C )
Fig 1. Normalized total power dissipation as a
function of mounting base temperature.
250
ID
(A)
03nh38
200
150
100
Capped at 100 A due to package
50
0
0 50
VGS ≥ 5 V
100 150 200
Tmb (˚C)
Fig 2. Continuous drain current as a function of
mounting base temperature.
104
03nh36
ID
(A)
103
Limit RDSon = VDS / ID
tp = 10 µ s
102 100 µ s
Capped at 100 A due to package
1 ms
DC 10 ms
10 100 ms
1
10-1
1
10
VDS (V)
102
Tmb = 25 °C; IDM single pulse.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 12049
Product data
Rev. 04 — 14 November 2003
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
3 of 16
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BUK99E3R2-40B | TrenchMOS logic level FET | NXP Semiconductors |
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