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Номер произв BUK9K52-60E
Описание Dual N-channel TrenchMOS logic level FET
Производители NXP Semiconductors
логотип NXP Semiconductors логотип 



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BUK9K52-60E Даташит, Описание, Даташиты
BUK9K52-60E
Dual N-channel TrenchMOS logic level FET
17 June 2013
Product data sheet
1. General description
Dual logic level N-channel MOSFET in a LFPAK56D package using TrenchMOS
technology. This product has been designed and qualified to AEC Q101 standard for use
in high performance automotive applications.
2. Features and benefits
Q101 compliant
Repetitive avalanche rated
Suitable for thermally demanding environments due to 175 °C rating
True logic level gate with VGS(th) > 0.5 V @ 175 °C
3. Applications
12 V Automotive systems
Motors, lamps and solenoid control
Start-stop micro-hybrid applications
Transmission control
Ultra high performance power switching
4. Quick reference data
Table 1. Quick reference data
Symbol
Parameter
Conditions
VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C
ID
drain current
VGS = 5 V; Tmb = 25 °C; Fig. 1
Ptot total power dissipation Tmb = 25 °C; Fig. 2
Static characteristics FET1 and FET2
RDSon
drain-source on-state VGS = 5 V; ID = 5 A; Tj = 25 °C; Fig. 12
resistance
Dynamic characteristics FET1 and FET2
QGD
gate-drain charge
ID = 5 A; VDS = 48 V; VGS = 5 V;
Tj = 25 °C; Fig. 14; Fig. 15
Min Typ Max Unit
- - 60 V
- - 16 A
- - 32 W
-
47.3 55
- 2.3 - nC
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BUK9K52-60E Даташит, Описание, Даташиты
NXP Semiconductors
BUK9K52-60E
Dual N-channel TrenchMOS logic level FET
5. Pinning information
Table 2. Pinning information
Pin Symbol Description
1 S1 source1
2 G1 gate1
3 S2 source2
4 G2 gate2
5 D2 drain2
6 D2 drain2
7 D1 drain1
8 D1 drain1
Simplified outline
8765
Graphic symbol
D1 D1
D2 D2
1234
LFPAK56D (SOT1205)
S1 G1 S2 G2
mbk725
6. Ordering information
Table 3. Ordering information
Type number
Package
Name
BUK9K52-60E
LFPAK56D
Description
Plastic single ended surface mounted package (LFPAK56D); 8
leads
Version
SOT1205
7. Marking
Table 4. Marking codes
Type number
BUK9K52-60E
Marking code
9526E
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
VDS drain-source voltage Tj ≥ 25 °C; Tj ≤ 175 °C
VDGR
drain-gate voltage
RGS = 20 kΩ; Tj ≥ 25 °C; Tj ≤ 175 °C
VGS gate-source voltage
Tj ≤ 175 °C; DC
Tj ≤ 175 °C; Pulsed
ID drain current
Tmb = 25 °C; VGS = 5 V; Fig. 1
Tmb = 100 °C; VGS = 5 V; Fig. 1
IDM peak drain current
Tmb = 25 °C; pulsed; tp ≤ 10 µs; Fig. 4
BUK9K52-60E
All information provided in this document is subject to legal disclaimers.
Product data sheet
17 June 2013
[1][2]
Min Max Unit
- 60 V
- 60 V
-10 10
V
-15 15
V
- 16 A
- 11 A
- 64 A
© NXP B.V. 2013. All rights reserved
2 / 13







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BUK9K52-60E Даташит, Описание, Даташиты
NXP Semiconductors
BUK9K52-60E
Dual N-channel TrenchMOS logic level FET
Symbol
Parameter
Ptot total power dissipation
Tstg storage temperature
Tj junction temperature
Tsld(M)
peak soldering temperature
Source-drain diode FET1 and FET2
IS source current
ISM peak source current
Avalanche Ruggedness FET1 and FET2
EDS(AL)S
non-repetitive drain-source
avalanche energy
Conditions
Tmb = 25 °C; Fig. 2
Tmb = 25 °C
pulsed; tp ≤ 10 µs; Tmb = 25 °C
ID = 16 A; Vsup ≤ 60 V; VGS = 5 V;
Tj(init) = 25 °C; Fig. 3
Min Max Unit
- 32 W
-55 175 °C
-55 175 °C
- 260 °C
- 16 A
- 64 A
[3][4] -
11.9 mJ
[1] Accumulated Pulse duration up to 50 hours delivers zero defect ppm
[2] Significantly longer life times are achieved by lowering Tj and or VGS
[3] Refer to application note AN10273 for further information
[4] Single-pulse avalanche rating limited by maximum junction temperature of 175 °C
20
ID
(A)
16
003aaj559
120
Pder
(%)
03aa16
80
12
8
40
4
0
0 30 60 90 120 150 180
Tj (°C)
Fig. 1. Continuous drain current as a function of
mounting base temperature
0
0 50 100 150 200
Tmb (°C)
Fig. 2. Normalized total power dissipation as a
function of mounting base temperature
BUK9K52-60E
Product data sheet
All information provided in this document is subject to legal disclaimers.
17 June 2013
© NXP B.V. 2013. All rights reserved
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