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AT45DB321D PDF даташит

Спецификация AT45DB321D изготовлена ​​​​«Adesto» и имеет функцию, называемую «2.5V or 2.7V DataFlash».

Детали детали

Номер произв AT45DB321D
Описание 2.5V or 2.7V DataFlash
Производители Adesto
логотип Adesto логотип 

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AT45DB321D Даташит, Описание, Даташиты
AT45DB321D
32Mb, 2.5V or 2.7V
DataFlash
DATASHEET
(NOT RECOMMENDED FOR NEW DESIGNS. USE AT45DB321E.)
Features
Single 2.5V - 3.6V or 2.7V - 3.6V supply
RapidSserial interface: 66MHz maximum clock frequency
SPI compatible modes 0 and 3
User configurable page size
512 bytes per page
528 bytes per page
Page size can be factory preconfigured for 512 bytes
Page program operation
Intelligent programming operation
8,192 pages (512/528 bytes/page) main memory
Flexible erase options
Page erase (512 bytes)
Block erase (4KB)
Sector erase (64KB)
Chip erase (32Mb)
Two SRAM data buffers (512/528 bytes)
Allows receiving data while reprogramming the flash array
Continuous read capability through entire array
Ideal for code shadowing applications
Low power dissipation
7mA active read current ,typical
25μA standby current, typical
15μA deep power down, typical
Hardware and software data protection features
Individual sector
Sector lockdown for secure code and data storage
Individual sector
Security: 128-byte security register
64-byte user programmable space
Unique 64-byte device identifier
JEDEC standard manufacturer and device ID read
100,000 program/erase cycles per page, minimum
Data retention: 20 years
Industrial temperature range
Green (Pb/halide-free/RoHS compliant) packaging options
3597T–DFLASH–11/2013









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AT45DB321D Даташит, Описание, Даташиты
1. Description
The AT45DB321D is a 2.5V or 2.7V, serial interface, sequential access flash memory ideally suited for a wide variety of digital
voice-, image-, program code-, and data-storage applications. The AT45DB321D supports the RapidS serial interface for
applications requiring very high speed operations. The RapidS serial interface is SPI compatible for frequencies up to 66MHz.
The 34,603,008-bits of memory are organized as 8,192 pages of 512 bytes or 528 bytes each. In addition to the main memory,
the AT45DB321D also contains two SRAM buffers of 512/528 bytes each. These buffers allow the receiving of data while a
page in the main memory is being reprogrammed, as well as the writing of a continuous data stream. EEPROM (electrically
erasable and programmable read-only memory) emulation (bit or byte alterability) is easily handled with a self-contained,
three-step read-modify-write operation. Unlike conventional flash memories, which are accessed randomly with multiple
address lines and a parallel interface, DataFlash® devices use a RapidS serial interface to sequentially access its data. The
simple sequential access dramatically reduces active pin count, facilitates hardware layout, increases system reliability,
minimizes switching noise, and reduces package size. The device is optimized for use in many commercial and industrial
applications where high density, low pin count, low voltage and low power are essential.
To allow for simple, in-system reprogrammability, the AT45DB321D does not require high input voltages for programming. The
device operates from a single power supply, 2.7V to 3.6V, for both the program and read operations. The AT45DB321D is
enabled through the chip select pin (CS) and accessed via a three-wire interface consisting of the serial input (SI), serial output
(SO), and serial clock (SCK) lines.
All programming and erase cycles are self timed.
Figure 1-1. Pin configurations and pinouts.
MLF(1) (VDFN)
Top View
SOIC
Top View
SI 1
SCK 2
RESET 3
CS 4
8 SO
7 GND
6 VCC
5 WP
Note:
1. The metal pad on the bottom of
the MLF package is floating.
This pad can be a “No Connect” or
connected to GND.
BGA Package Ball-out
Top View
SI
SCK
RESET
CS
1
2
3
4
8 SO
7 GND
6 VCC
5 WP
TSOP: Type 1
Top View
12 3 4 5
A
NC NC NC NC
B
NC SCK GND VCC NC
C
NC CS RDY/BSY WP NC
D
NC SO
SI RESET NC
E
NC NC NC NC NC
RDY/BUSY
RESET
WP
NC
NC
VCC
GND
NC
NC
NC
CS
SCK
SI
SO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 NC
27 NC
26 NC
25 NC
24 NC
23 NC
22 NC
21 NC
20 NC
19 NC
18 NC
17 NC
16 NC
15 NC
Note:
TSOP package is not recommended for new designs.
Future die shrinks will support 8-pin packages only.
AT45DB321D [DATASHEET]
3597T–DFLASH–11/2013
2









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AT45DB321D Даташит, Описание, Даташиты
Table 1-1. Pin Configurations
Symbol
CS
SCK
SI
SO
WP
RESET
RDY/BUSY
VCC
GND
Name and Function
Chip Select: Asserting the CS pin selects the device. When the CS pin is deasserted, the
device will be deselected and normally be placed in the standby mode (not deep power-
down mode), and the output pin (SO) will be in a high-impedance state. When the device
is deselected, data will not be accepted on the input pin (SI).
A high-to-low transition on the CS pin is required to start an operation, and a low-to-high
transition is required to end an operation. When ending an internally self-timed operation
such as a program or erase cycle, the device will not enter the standby mode until the
completion of the operation.
Serial Clock: This pin is used to provide a clock to the device, and is used to control the
flow of data to and from the device. Command, address, and input data present on the SI
pin are always latched on the rising edge of SCK, while output data on the SO pin are
always clocked out on the falling edge of SCK.
Serial Input: The SI pin is used to shift data into the device. The SI pin is used for all data
input, including command and address sequences. Data on the SI pin are always latched
on the rising edge of SCK.
Serial Output: The SO pin is used to shift data out from the device. Data on the SO pin
are always clocked out on the falling edge of SCK.
Write Protect: When the WP pin is asserted, all sectors specified for protection by the
sector protection register will be protected against program and erase operations,
regardless of whether the enable sector protection command has been issued or not. The
WP pin functions independently of the software controlled protection method. After the
WP pin goes low, the content of the sector protection register cannot be modified.
If a program or erase command is issued to the device while the WP pin is asserted, the
device will simply ignore the command and perform no operation. The device will return to
the idle state once the CS pin has been deasserted. The enable sector protection
command and sector lockdown command, however, will be recognized by the device
when the WP pin is asserted.
The WP pin is internally pulled high, and may be left floating if hardware controlled
protection will not be used. However, it is recommended that the WP pin also be
externally connected to VCC whenever possible.
Reset: A low state on the reset pin (RESET) will terminate the operation in progress and
reset the internal state machine to an idle state. The device will remain in the reset
condition as long as a low level is present on the RESET pin. Normal operation can
resume once the RESET pin is brought back to a high level.
The device incorporates an internal power-on reset circuit, and so there are no restrictions
on the RESET pin during power-on sequences. If this pin and feature are not utilized, it is
recommended that the RESET pin be driven high externally.
Ready/Busy: This open drain output pin will be driven low when the device is busy in an
internally self-timed operation. This pin, which is normally in a high state (through
an external pull-up resistor), will be pulled low during programming/erase operations,
compare operations, and page-to-buffer transfers.
The busy status indicates that the flash memory array and one of the buffers cannot be
accessed; read and write operations to the other buffer can still be performed.
Device Power Supply: The VCC pin is used to supply the source voltage to the device.
Operations at invalid VCC voltages may produce spurious results and should not be
attempted.
Ground: The ground reference for the power supply. GND should be connected to the
system ground.
Asserted
State
Low
Low
Low
Type
Input
Input
Input
Output
Input
Input
Output
Power
Ground
AT45DB321D [DATASHEET]
3597T–DFLASH–11/2013
3










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