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AT45DB041D-MU-SL955 PDF даташит

Спецификация AT45DB041D-MU-SL955 изготовлена ​​​​«Adesto» и имеет функцию, называемую «4-megabit 2.5-volt or 2.7-volt DataFlash».

Детали детали

Номер произв AT45DB041D-MU-SL955
Описание 4-megabit 2.5-volt or 2.7-volt DataFlash
Производители Adesto
логотип Adesto логотип 

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AT45DB041D-MU-SL955 Даташит, Описание, Даташиты
Features
Single 2.5V or 2.7V to 3.6V Supply
RapidSTM Serial Interface: 66MHz Maximum Clock Frequency
– SPI Compatible Modes 0 and 3
User Configurable Page Size
– 256-Bytes per Page
– 264-Bytes per Page
– Page Size Can Be Factory Pre-configured for 256-Bytes
Page Program Operation
– Intelligent Programming Operation
– 2,048 Pages (256-/264-Bytes/Page) Main Memory
Flexible Erase Options
– Page Erase (256-Bytes)
– Block Erase (2-Kbytes)
– Sector Erase (64-Kbytes)
– Chip Erase (4Mbits)
Two SRAM Data Buffers (256-, 264-Bytes)
– Allows Receiving of Data while Reprogramming the Flash Array
Continuous Read Capability through Entire Array
– Ideal for Code Shadowing Applications
Low-power Dissipation
– 7mA Active Read Current Typical
– 25μA Standby Current Typical
– 15μA Deep Power-down Typical
Hardware and Software Data Protection Features
– Individual Sector
Sector Lockdown for Secure Code and Data Storage
– Individual Sector
Security: 128-byte Security Register
– 64-byte User Programmable Space
– Unique 64-byte Device Identifier
JEDEC Standard Manufacturer and Device ID Read
100,000 Program/Erase Cycles Per Page Minimum
Data Retention – 20 Years
Industrial Temperature Range
Green (Pb/Halide-free/RoHS Compliant) Packaging Options
4-megabit
2.5-volt or
2.7-volt
DataFlash®
AT45DB041D
(Not recommended for
new designs. Use
AT45DB041E.)
1. Description
The AT45DB041D is a 2.5V or 2.7V, serial-interface Flash memory ideally suited for a
wide variety of digital voice-, image-, program code- and data-storage applications.
The AT45DB041D supports RapidS serial interface for applications requiring very
high speed operations. RapidS serial interface is SPI compatible for frequencies up to
66MHz. Its 4,325,376-bits of memory are organized as 2,048 pages of 256-bytes or
264-bytes each. In addition to the main memory, the AT45DB041D also contains two
SRAM buffers of 256-/264-bytes each. The buffers allow the receiving of data while a
page in the main Memory is being reprogrammed, as well as writing a continuous data
stream. EEPROM emulation (bit or byte alterability) is easily handled with a self-con-
tained three step read-modify-write operation. Unlike conventional Flash memories
that are accessed randomly with multiple address lines and a parallel interface, the
DataFlash uses a RapidS serial interface to sequentially access its data. The simple
sequential access dramatically
3595T–DFLASH–8/2013









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AT45DB041D-MU-SL955 Даташит, Описание, Даташиты
reduces active pin count, facilitates hardware layout, increases system reliability, minimizes
switching noise, and reduces package size. The device is optimized for use in many commercial
and industrial applications where high-density, low-pin count, low-voltage and low-power are
essential.
To allow for simple in-system reprogrammability, the AT45DB041D does not require high input
voltages for programming. The device operates from a single power supply, 2.5V to 3.6V or 2.7V
to 3.6V, for both the program and read operations. The AT45DB041D is enabled through the
chip select pin (CS) and accessed via a three-wire interface consisting of the Serial Input (SI),
Serial Output (SO), and the Serial Clock (SCK).
All programming and erase cycles are self-timed.
2. Pin Configurations and Pinouts
Table 2-1. Pin Configurations
Symbol
CS
SCK
SI
SO
WP
RESET
VCC
GND
Name and Function
Chip Select: Asserting the CS pin selects the device. When the CS pin is deasserted, the device will be deselected
and normally be placed in the standby mode (not Deep Power-Down mode), and the output pin (SO) will be in a
high-impedance state. When the device is deselected, data will not be accepted on the input pin (SI).
A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition is required to
end an operation. When ending an internally self-timed operation such as a program or erase cycle, the device
will not enter the standby mode until the completion of the operation.
Serial Clock: This pin is used to provide a clock to the device and is used to control the flow of data to and from
the device. Command, address, and input data present on the SI pin is always latched on the rising edge of SCK,
while output data on the SO pin is always clocked out on the falling edge of SCK.
Serial Input: The SI pin is used to shift data into the device. The SI pin is used for all data input including
command and address sequences. Data on the SI pin is always latched on the rising edge of SCK.
Serial Output: The SO pin is used to shift data out from the device. Data on the SO pin is always clocked out on
the falling edge of SCK.
Write Protect: When the WP pin is asserted, all sectors specified for protection by the Sector Protection Register
will be protected against program and erase operations regardless of whether the Enable Sector Protection
command has been issued or not. The WP pin functions independently of the software controlled protection method.
After the WP pin goes low, the content of the Sector Protection Register cannot be modified.
If a program or erase command is issued to the device while the WP pin is asserted, the device will simply ignore
the command and perform no operation. The device will return to the idle state once the CS pin has been
deasserted. The Enable Sector Protection command and Sector Lockdown command, however, will be
recognized by the device when the WP pin is asserted.
The WP pin is internally pulled-high and may be left floating if hardware controlled protection will not be used.
However, it is recommended that the WP pin also be externally connected to VCC whenever possible.
Reset: A low state on the reset pin (RESET) will terminate the operation in progress and reset the internal state
machine to an idle state. The device will remain in the reset condition as long as a low level is present on the RESET
pin. Normal operation can resume once the RESET pin is brought back to a high level.
The device incorporates an internal power-on reset circuit, so there are no restrictions on the RESET pin during
power-on sequences. If this pin and feature are not utilized it is recommended that the RESET pin be driven high
externally.
Device Power Supply: The VCC pin is used to supply the source voltage to the device.
Operations at invalid VCC voltages may produce spurious results and should not be attempted.
Ground: The ground reference for the power supply. GND should be connected to the system ground.
Asserted
State
Low
Low
Low
Type
Input
Input
Input
Output
Input
Input
Power
Ground
2 AT45DB041D
3595T–DFLASH–8/2013









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AT45DB041D-MU-SL955 Даташит, Описание, Даташиты
AT45DB041D
Figure 2-1. MLF (VDFN)Top View
SI 1
SCK 2
RESET 3
CS 4
8 SO
7 GND
6 VCC
5 WP
Figure 2-2. SOIC Top View
SI
SCK
RESET
CS
1
2
3
4
8 SO
7 GND
6 VCC
5 WP
Note: 1. The metal pad on the bottom of the MLF package is floating. This pad can be a “No Connect” or connected to GND
3. Block Diagram
WP FLASH MEMORY ARRAY
PAGE (256-/264-BYTES)
SCK
CS
RESET
VCC
GND
BUFFER 1 (256-/264-BYTES)
BUFFER 2 (256-/264-BYTES)
I/O INTERFACE
SI SO
3595T–DFLASH–8/2013
3










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