DataSheet26.com

AT25DN256-MAHFGP-T PDF даташит

Спецификация AT25DN256-MAHFGP-T изготовлена ​​​​«Adesto» и имеет функцию, называемую «2.3V Minimum SPI Serial Flash Memory».

Детали детали

Номер произв AT25DN256-MAHFGP-T
Описание 2.3V Minimum SPI Serial Flash Memory
Производители Adesto
логотип Adesto логотип 

30 Pages
scroll

No Preview Available !

AT25DN256-MAHFGP-T Даташит, Описание, Даташиты
AT25DN256
256-Kbit, 2.3V Minimum
SPI Serial Flash Memory with Dual-Read Support
Features
PRELIMINARY DATASHEET
Single 2.3V - 3.6V Supply
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 and 3
Supports Dual Output Read
104MHz Maximum Operating Frequency
Clock-to-Output (tV) of 6ns
Flexible, Optimized Erase Architecture for Code + Data Storage Applications
Uniform 256-Byte Page erase
Uniform 4-Kbyte Block Erase
Uniform 32-Kbyte Block Erase
Full Chip Erase
Hardware Controlled Locking of Protected Sectors via WP Pin
128-Byte Programmable OTP Security Register
Flexible Programming
Byte/Page Program (1 to 256 Bytes)
Fast Program and Erase Times
1.5ms Typical Page Program (256 Bytes) Time
40ms Typical 4-Kbyte Block Erase Time
320ms Typical 32-Kbyte Block Erase Time
Automatic Checking and Reporting of Erase/Program Failures
Software Controlled Reset
JEDEC Standard Manufacturer and Device ID Read Methodology
Low Power Dissipation
350nA Ultra Deep Power Down current (Typical)
5µA Deep Power-Down Current (Typical)
25uA Standby current (Typical)
6mA Active Read Current (Typical)
Endurance: 100,000 Program/Erase Cycles
Data Retention: 20 Years
Complies with Full Industrial Temperature Range
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
8-lead SOIC (150-mil)
8-pad Ultra Thin DFN (2 x 3 x 0.6mm)
8-lead TSSOP Package
DS-25DN256–039B–5/2014









No Preview Available !

AT25DN256-MAHFGP-T Даташит, Описание, Даташиты
1. Description
The Adesto® AT25DN256 is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer
based applications in which program code is shadowed from Flash memory into embedded or external RAM for execution. The
flexible erase architecture of the AT25DN256, with its page erase granularity it is ideal for data storage as well, eliminating the
need for additional data storage devices.
The erase block sizes of the AT25DN256 have been optimized to meet the needs of today's code and data storage applications.
By optimizing the size of the erase blocks, the memory space can be used much more efficiently. Because certain code modules
and data storage segments must reside by themselves in their own erase regions, the wasted and unused memory space that
occurs with large sectored and large block erase Flash memory devices can be greatly reduced. This increased memory space
efficiency allows additional code routines and data storage segments to be added while still maintaining the same overall device
density.
The device also contains a specialized OTP (One-Time Programmable) Security Register that can be used for purposes such as
unique device serialization, system-level Electronic Serial Number (ESN) storage, locked key storage, etc.
Specifically designed for use in many different systems, the AT25DN256 supports read, program, and erase operations with a
wide supply voltage range of 2.3V to 3.6V. No separate voltage is required for programming and erasing.
2. Pin Descriptions and Pinouts
Table 2-1. Pin Descriptions
Symbol
CS
SCK
SI (I/O0)
SO
(I/O1)
Name and Function
CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is deasserted, the
device will be deselected and normally be placed in standby mode (not Deep Power-Down mode),
and the SO pin will be in a high-impedance state. When the device is deselected, data will not be
accepted on the SI pin.
A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition
is required to end an operation. When ending an internally self-timed operation such as a program
or erase cycle, the device will not enter the standby mode until the completion of the operation.
SERIAL CLOCK: This pin is used to provide a clock to the device and is used to control the flow of
data to and from the device. Command, address, and input data present on the SI pin is always
latched in on the rising edge of SCK, while output data on the SO pin is always clocked out on the
falling edge of SCK.
SERIAL INPUT: The SI pin is used to shift data into the device. The SI pin is used for all data input
including command and address sequences. Data on the SI pin is always latched in on the rising
edge of SCK.
With the Dual-Output Read commands, the SI Pin becomes an output pin (I/O0) in conjunction with
other pins to allow two bits of data on (I/O1-0) to be clocked out on every falling edge of SCK.
To maintain consistency with the SPI nomenclature, the SI (I/O0) pin will be referenced as the SI
pin unless specifically addressing the Dual-I/O modes in which case it will be referenced as I/O0.
Data present on the SI pin will be ignored whenever the device is deselected (CS is deasserted).
SERIAL OUTPUT: The SO pin is used to shift data out from the device. Data on the SO pin is
always clocked out on the falling edge of SCK.
With the Dual-Output Read commands, the SO Pin remains an output pin (I/O1) in conjunction with
other pins to allow two bits of data on (I/O1-0) to be clocked out on every falling edge of SCK.
To maintain consistency with the SPI nomenclature, the SO (I/O1) pin will be referenced as the SO
pin unless specifically addressing the Dual-I/O modes in which case it will be referenced as I/O1.
The SO pin will be in a high-impedance state whenever the device is deselected (CS is
deasserted).
Asserted
State
Low
-
-
-
Type
Input
Input
Input/
Output
Input/
Output
AT25DN256
DS-25DN256–039B–5/2014
2









No Preview Available !

AT25DN256-MAHFGP-T Даташит, Описание, Даташиты
Table 2-1. Pin Descriptions (Continued)
Symbol
WP
HOLD
VCC
GND
Name and Function
WRITE PROTECT: The WP pin controls the hardware locking feature of the device. Please refer
to “Protection Commands and Features” on page 12 for more details on protection features and
the WP pin.
The WP pin is internally pulled-high and may be left floating if hardware controlled protection will
not be used. However, it is recommended that the WP pin also be externally connected to VCC
whenever possible.
HOLD: The HOLD pin is used to temporarily pause serial communication without deselecting or
resetting the device. While the HOLD pin is asserted, transitions on the SCK pin and data on the
SI pin will be ignored, and the SO pin will be in a high-impedance state.
The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold
condition to start. A Hold condition pauses serial communication only and does not have an
effect on internally self-timed operations such as a program or erase cycle. Please refer to
“Hold” on page 26 for additional details on the Hold operation.
The HOLD pin is internally pulled-high and may be left floating if the Hold function will not be used.
However, it is recommended that the HOLD pin also be externally connected to VCC whenever
possible.
DEVICE POWER SUPPLY: The VCC pin is used to supply the source voltage to the device.
Operations at invalid VCC voltages may produce spurious results and should not be attempted.
GROUND: The ground reference for the power supply. GND should be connected to the system
ground.
Asserted
State
Low
Low
-
-
Type
Input
Input
Power
Power
Table 2-2. Pinouts
Figure 2-1. 8-SOIC Top View
Figure 2-3. 8-UDFN (Top View)
CS
SO
WP
GND
1
2
3
4
8 VCC
7 HOLD
6 SCK
5 SI
CS 1
SO 2
WP 3
GND 4
8 VCC
7 HOLD
6 SCK
5 SI
Figure 2-2. 8-TSSOP Top View
CS
SO
WP
GND
1
2
3
4
8 VCC
7 HOLD
6 SCK
5 SI
AT25DN256
DS-25DN256–039B–5/2014
3










Скачать PDF:

[ AT25DN256-MAHFGP-T.PDF Даташит ]

Номер в каталогеОписаниеПроизводители
AT25DN256-MAHFGP-T2.3V Minimum SPI Serial Flash MemoryAdesto
Adesto

Номер в каталоге Описание Производители
TL431

100 мА, регулируемый прецизионный шунтирующий регулятор

Unisonic Technologies
Unisonic Technologies
IRF840

8 А, 500 В, N-канальный МОП-транзистор

Vishay
Vishay
LM317

Линейный стабилизатор напряжения, 1,5 А

STMicroelectronics
STMicroelectronics

DataSheet26.com    |    2020    |

  Контакты    |    Поиск