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AX1250ES PDF даташит

Спецификация AX1250ES изготовлена ​​​​«AXElite» и имеет функцию, называемую «2A Sink/Source Bus Termination Regulator».

Детали детали

Номер произв AX1250ES
Описание 2A Sink/Source Bus Termination Regulator
Производители AXElite
логотип AXElite логотип 

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AX1250ES Даташит, Описание, Даташиты
AX1250ES
2A Sink/Source Bus Termination Regulator
GENERAL DESCRIPTION
The AX1250ES is a simple, cost-effective and high-speed linear regulator designed
to generate termination voltage in double data rate (DDR) memory system to comply with
the JEDEC SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 and
SCSI-3 etc. devices requirements. The regulator is capable of actively sinking or sourcing
up to 2A while regulating an output voltage to within 40mV. The output termination voltage
cab be tightly regulated to track 1/2VDDQ by two external voltage divider resistors or the
desired output voltage can be programmed by externally forcing the REFEN pin voltage.
The AX1250ES also incorporates a high-speed differential amplifier to provide
ultra-fast response in line/load transient. Other features include extremely low initial offset
voltage, excellent load regulation, current limiting in bi-directions and on-chip thermal
shut-down protection.
The AX1250ES are available in the SOP-8L-EP (Exposed Pad) surface mount
packages.
FEATURES
- Ideal for DDR-I, DDR-II and DDR-III VTT Applications
- Sink and Source 2A Continuous Current
- Integrated Power MOSFETs
- Generates Termination Voltage for SSTL_2, SSTL _18, HSTL, SCSI-2 and SCSI-3
Interfaces.
- High Accuracy Output Voltage at Full-Load
- Output Voltage traces REFEN Pin Voltage.
- Low External Component Count
- Shutdown for Suspend to RAM (STR) Functionality with High-Impedance Output
- Current Limiting Protection
- Thermal Shutdown Protection
- SOP-8L with exposed pad Pb-Free Package.
1/9
Axelite Confidential Materials, do not copy or distribute without written consent.
Rev.1.3 Aug.24, 2011









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AX1250ES Даташит, Описание, Даташиты
AX1250ES
BLOCK DIAGRAM
VCNTL
VREF
Enable
EN
VREF
Thermal THSD
Shutdown
Current-
Limit
Error
Amplifier
and
Soft-Start
Power-On-
Reset
POR
VIN
VOUT
GND
PIN ASSIGNMENT
The package of AX1250ES is SOP-8L-EP; the pin assignment is given by:
Name
VIN
GND
REFEN
VOUT
VCNTL
NC
Description
Input Voltage pin
Ground pin
Reference voltage input and chip
enable pin
Output Voltage pin
Supply Input and Gate drive
voltage pin
No connect pin
ORDER/MARKING INFORMATION
Order Information
AX 1250 XX X
Package Type
ES: SOP-8L-EP
Packing
Blank : Tube
A : Taping
Top Marking
2/9
Axelite Confidential Materials, do not copy or distribute without written consent.
Rev.1.3 Aug.24, 2011









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AX1250ES Даташит, Описание, Даташиты
AX1250ES
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Characteristics
Symbol
Rating
Unit
VIN Supply Voltage
VIN 6 V
Control Voltage
VCNTL 6 V
Power Dissipation
PD Internally Limited W
Storage Temperature Range
TST -65 to +150 °C
Thermal Resistance from Junction to case
θJC 15 °C/W
Thermal Resistance from Junction to ambient
θJA 40 °C/W
Note: θJA is measured with the PCB copper area (need connect to Exposed pad) of approximately 1.5 in2
(Multi-layer).
OPERATING RATTING
Parameter
Symbol
Value
Input Voltage
Control Voltage
Ambient Temperature
Junction Temperature
VIN
VCNTL
TA
TJ
1.3 to VCNTL
5 or 3.3
-40 to +85
-40 to +125
Note: VOS offset is the voltage measurement defined as VOUT subtracted from VREFEN.
Unit
V
V
°C
°C
ELECTRICAL CHARACTERISTICS
VIN=2.5V, VCNTL=3.3V, VREFEN=1.25V, COUT=10µF (Ceramic), TA=25ºC, unless otherwise
specified
Characteristics
Gate Drive Voltage Range
Symbol
VCNTL
Conditions
Min Typ Max Units
- 3.3 5.5 V
POR Threshold
VCNTLRTH
- 2.5 - V
POR Hysteresis
VCNTL
- 0.1 - V
Input Voltage
VIN
1.3 - VCNTL V
Quiescent Current
ICNTL IOUT=0A
- 1 3 mA
Standby Current
ISTBY IOUT=0A, VREFEN=0V
- 1 10 μA
Output Offset Voltage (Note1)
VOS IOUT=0A
-20 - +20 mV
Load Regulation (Note2)
VLOAD IOUT=±2.0A
- 0.5 ±2 %
Shutdown Threshold
VIH Enable, REFEN Rising
VIL
Shutdown, REFEN
Falling
0.7 - -
- - 0.2
V
V
Current Limit
ICL-Source Sourcing
ICL-Sink Sinking
2.2 - -
2.2 - -
A
A
Soft-Start Period
TSS VOUT=1.25V
- 1.5 - mS
Thermal Shutdown
TSD
- 160 - °C
Thermal Shutdown Hysterisis
TSDH
- 30 - °C
Note 1: VOS offset is the voltage measurement defined as VOUT subtracted from VREFEN.
Note 2: Regulation is measured at constant junction temperature by using a 5ms current pulse. Devices are
tested for load regulation in the load range from 0A to 2A.
3/9
Axelite Confidential Materials, do not copy or distribute without written consent.
Rev.1.3 Aug.24, 2011










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