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PDF AD9778 Data sheet ( Hoja de datos )
| Número de pieza | AD9778 | |
| Descripción | Digital-to-Analog Converters | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD9778 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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Dual 12-/14-/16-Bit,
1 GSPS, Digital-to-Analog Converters
AD9776/AD9778/AD9779
FEATURES
Low power: 1.0 W @ 1 GSPS, 600 mW @ 500 MSPS,
full operating conditions
SFDR = 78 dBc to fOUT = 100 MHz
Single carrier WCDMA ACLR = 79 dBc @ 80 MHz IF
Analog output: adjustable 8.7 mA to 31.7 mA,
RL = 25 Ω to 50 Ω
Novel 2×, 4×, and 8× interpolator/coarse complex modulator
allows carrier placement anywhere in DAC bandwidth
Auxiliary DACs allow control of external VGA and offset control
Multiple chip synchronization interface
High performance, low noise PLL clock multiplier
Digital inverse sinc filter
100-lead, exposed paddle TQFP package
APPLICATIONS
Wireless infrastructure
WCDMA, CDMA2000, TD-SCDMA, WiMax, GSM
Digital high or low IF synthesis
Internal digital upconversion capability
Transmit diversity
Wideband communications: LMDS/MMDS, point-to-point
GENERAL DESCRIPTION
The AD9776/AD9778/AD9779 are dual, 12-/14-/16-bit, high
dynamic range, digital-to-analog converters (DACs) that pro-
vide a sample rate of 1 GSPS, permitting multicarrier generation
up to the Nyquist frequency. They include features optimized
for direct conversion transmit applications, including complex
digital modulation, and gain and offset compensation. The DAC
outputs are optimized to interface seamlessly with analog quad-
rature modulators such as the AD8349. A serial peripheral interface
(SPI®) provides for programming/readback of many internal
parameters. Full-scale output current can be programmed over a
range of 10 mA to 30 mA. The devices are manufactured on an
advanced 0.18 μm CMOS process and operate on 1.8 V and
3.3 V supplies for a total power consumption of 1.0 W. They are
enclosed in 100-lead TQFP packages.
PRODUCT HIGHLIGHTS
1. Ultralow noise and intermodulation distortion (IMD)
enable high quality synthesis of wideband signals from
baseband to high intermediate frequencies.
2. A proprietary DAC output switching technique enhances
dynamic performance.
3. The current outputs are easily configured for various
single-ended or differential circuit topologies.
4. CMOS data input interface with adjustable set up and hold.
5. Novel 2×, 4×, and 8× interpolator/coarse complex
modulator allows carrier placement anywhere in DAC
bandwidth.
COMPLEX I AND Q
DC
FPGA/ASIC/DSP
TYPICAL SIGNAL CHAIN
QUADRATURE
MODULATOR/
MIXER/
AMPLIFIER
DC
LO
DIGITAL INTERPOLATION FILTERS
I DAC
Q DAC
POST DAC
ANALOG FILTER
A
AD9779
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2005–2007 Analog Devices, Inc. All rights reserved.
1 page  
Parameter
8× Mode, fDAC/4 Modulation,
fDAC = 1 GSPS, IF = 262.5 MHz
Power-Down Mode
Power Supply Rejection Ratio,
AVDD33
OPERATING RANGE
1 Based on a 10 kΩ external resistor.
Min
−0.3
−40
AD9776
Typ Max
980
2 3.7
+0.3
+25 +85
AD9776/AD9778/AD9779
AD9778
Min Typ Max
980
2
−0.3
3.7
+0.3
−40 +25 +85
AD9779
Min Typ Max
980
2
−0.3
3.7
+0.3
−40 +25 +85
Unit
mW
mW
% FSR/V
°C
Rev. A | Page 5 of 56
5 Page 
AD9776/AD9778/AD9779
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
CVDD18 1
CVDD18 2
CGND 3
CGND 4
CLK+ 5
CLK– 6
CGND 7
CGND 8
CVDD18 9
CVDD18 10
CGND 11
AGND 12
SYNC_I+ 13
SYNC_I– 14
DGND 15
DVDD18 16
P1D<13> 17
P1D<12> 18
P1D<11> 19
P1D<10> 20
P1D<9> 21
DGND 22
DVDD18 23
P1D<8> 24
P1D<7> 25
PIN 1
ANALOG DOMAIN
DIGITAL DOMAIN
AD9778
TOP VIEW
(Not to Scale)
75 I120
74 VREF
73 IPTAT
72 AGND
71 IRQ
70 RESET
69 CSB
68 SCLK
67 SDIO
66 SDO
65 PLL_LOCK
64 DGND
63 SYNC_O+
62 SYNC_O–
61 DVDD33
60 DVDD18
59 NC
58 NC
57 P2D<0>
56 P2D<1>
55 P2D<2>
54 DGND
53 DVDD18
52 P2D<3>
51 P2D<4>
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC = NO CONNECT
Figure 4. AD9778 Pin Configuration
Table 7. AD9778 Pin Function Description
Pin
No. Mnemonic
Description
Pin
No.
1 CVDD18
1.8 V Clock Supply.
21
2 CVDD18
1.8 V Clock Supply.
22
3 CGND
4 CGND
5 CLK+1
6 CLK−1
7 CGND
Clock Common.
Clock Common.
Differential Clock Input.
Differential Clock Input.
Clock Common.
23
24
25
26
27
8 CGND
Clock Common.
28
9 CVDD18
1.8 V Clock Supply.
29
10 CVDD18
1.8 V Clock Supply.
30
11 CGND
12 AGND
13 SYNC_I+
14 SYNC_I−
Clock Common.
Analog Common.
Differential Synchronization Input.
Differential Synchronization Input.
31
32
33
34
15 DGND
Digital Common.
35
16 DVDD18
1.8 V Digital Supply.
36
17 P1D<13>
Port 1, Data Input D13 (MSB).
37
18 P1D<12>
19 P1D<11>
20 P1D<10>
Port 1, Data Input D12.
Port 1, Data Input D11.
Port 1, Data Input D10.
38
39
40
Rev. A | Page 11 of 56
Mnemonic
P1D<9>
DGND
DVDD18
P1D<8>
P1D<7>
P1D<6>
P1D<5>
P1D<4>
P1D<3>
P1D<2>
P1D<1>
DGND
DVDD18
P1D<0>
NC
NC
DATACLK
DVDD33
TXENABLE
P2D<13>
Description
Port 1, Data Input D9.
Digital Common.
1.8 V Digital Supply.
Port 1, Data Input D8.
Port 1, Data Input D7.
Port 1, Data Input D6.
Port 1, Data Input D5.
Port 1, Data Input D4.
Port 1, Data Input D3.
Port 1, Data Input D2.
Port 1, Data Input D1.
Digital Common.
1.8 V Digital Supply.
Port 1, Data Input D0 (LSB).
No Connect.
No Connect.
Data Clock Output.
3.3 V Digital Supply.
Transmit Enable.
Port 2, Data Input D13 (MSB).
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9778.PDF ] | |
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