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AD9776 PDF даташит

Спецификация AD9776 изготовлена ​​​​«Analog Devices» и имеет функцию, называемую «Digital-to-Analog Converters».

Детали детали

Номер произв AD9776
Описание Digital-to-Analog Converters
Производители Analog Devices
логотип Analog Devices логотип 

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AD9776 Даташит, Описание, Даташиты
Dual 12-/14-/16-Bit,
1 GSPS, Digital-to-Analog Converters
AD9776/AD9778/AD9779
FEATURES
Low power: 1.0 W @ 1 GSPS, 600 mW @ 500 MSPS,
full operating conditions
SFDR = 78 dBc to fOUT = 100 MHz
Single carrier WCDMA ACLR = 79 dBc @ 80 MHz IF
Analog output: adjustable 8.7 mA to 31.7 mA,
RL = 25 Ω to 50 Ω
Novel 2×, 4×, and 8× interpolator/coarse complex modulator
allows carrier placement anywhere in DAC bandwidth
Auxiliary DACs allow control of external VGA and offset control
Multiple chip synchronization interface
High performance, low noise PLL clock multiplier
Digital inverse sinc filter
100-lead, exposed paddle TQFP package
APPLICATIONS
Wireless infrastructure
WCDMA, CDMA2000, TD-SCDMA, WiMax, GSM
Digital high or low IF synthesis
Internal digital upconversion capability
Transmit diversity
Wideband communications: LMDS/MMDS, point-to-point
GENERAL DESCRIPTION
The AD9776/AD9778/AD9779 are dual, 12-/14-/16-bit, high
dynamic range, digital-to-analog converters (DACs) that pro-
vide a sample rate of 1 GSPS, permitting multicarrier generation
up to the Nyquist frequency. They include features optimized
for direct conversion transmit applications, including complex
digital modulation, and gain and offset compensation. The DAC
outputs are optimized to interface seamlessly with analog quad-
rature modulators such as the AD8349. A serial peripheral interface
(SPI®) provides for programming/readback of many internal
parameters. Full-scale output current can be programmed over a
range of 10 mA to 30 mA. The devices are manufactured on an
advanced 0.18 μm CMOS process and operate on 1.8 V and
3.3 V supplies for a total power consumption of 1.0 W. They are
enclosed in 100-lead TQFP packages.
PRODUCT HIGHLIGHTS
1. Ultralow noise and intermodulation distortion (IMD)
enable high quality synthesis of wideband signals from
baseband to high intermediate frequencies.
2. A proprietary DAC output switching technique enhances
dynamic performance.
3. The current outputs are easily configured for various
single-ended or differential circuit topologies.
4. CMOS data input interface with adjustable set up and hold.
5. Novel 2×, 4×, and 8× interpolator/coarse complex
modulator allows carrier placement anywhere in DAC
bandwidth.
COMPLEX I AND Q
DC
FPGA/ASIC/DSP
TYPICAL SIGNAL CHAIN
QUADRATURE
MODULATOR/
MIXER/
AMPLIFIER
DC
LO
DIGITAL INTERPOLATION FILTERS
I DAC
Q DAC
POST DAC
ANALOG FILTER
A
AD9779
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2005–2007 Analog Devices, Inc. All rights reserved.









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AD9776 Даташит, Описание, Даташиты
AD9776/AD9778/AD9779
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Typical Signal Chain......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
DC Specifications ......................................................................... 4
Digital Specifications ................................................................... 6
Digital Input Data Timing Specifications ................................. 7
AC Specifications.......................................................................... 7
Absolute Maximum Ratings............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution.................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Typical Performance Characteristics ........................................... 15
Terminology .................................................................................... 24
Theory of Operation ...................................................................... 25
Serial Peripheral Interface ......................................................... 25
MSB/LSB Transfers..................................................................... 26
REVISION HISTORY
3/07—Rev. 0 to Rev. A
Changes to Features.......................................................................... 1
Changes to Applications .................................................................. 1
Changes to General Product Highlights........................................ 1
Added Figure 1, Renumbered Figures Sequentially..................... 1
Changes to Table 1............................................................................ 4
Changes to Table 2............................................................................ 5
Changes to Table 3............................................................................ 5
Changes to Figure 53 and Figure 54............................................. 26
Changes to Table 12........................................................................ 29
Changes to Power Dissipation Section ........................................ 39
SPI Register Map ............................................................................ 27
Interpolation Filter Architecture .................................................. 31
Interpolation Filter Minimum and Maximum Bandwidth
Specifications .............................................................................. 35
Driving the REFCLK Input....................................................... 35
Internal PLL Clock Multiplier/Clock Distribution................ 36
Full-Scale Current Generation ................................................. 38
Power Dissipation....................................................................... 39
Power-Down and Sleep Modes................................................. 41
Interleaved Data Mode .............................................................. 41
Timing Information ................................................................... 41
Synchronization of Input Data to DATACLK
Output (Pin 37)........................................................................... 43
Synchronization of Input Data to the REFCLK Input (Pin 5
and Pin 6) with PLL Enabled or Disabled............................... 43
Evaluation Board Operation ......................................................... 46
Modifying the Evaluation Board to Use the AD8349 On-
Board Quadrature Modulator................................................... 48
Evaluation Board Schematics ................................................... 49
Outline Dimensions ....................................................................... 56
Ordering Guide .......................................................................... 56
Added Table 19, Renumbered Tables Sequentially .................... 41
Changes to Figure 92 and Figure 93............................................. 42
Changes to Figure 94...................................................................... 42
Added New Figure 95, Renumbered Figures Sequentially ....... 42
Changes to Synchronization of Input Data to the REFCLK Input
(Pin 5 and Pin 6) with PLL Enabled or Disabled Section ......... 43
Added New Figure 96, Renumbered Figures Sequentially ....... 43
Changes to Figure 106 ................................................................... 51
7/05—Revision 0: Initial Version
Rev. A | Page 2 of 56









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AD9776 Даташит, Описание, Даташиты
FUNCTIONAL BLOCK DIAGRAM
SYNC_O
SYNC_I
DATACLK_OUT
P1D(15:0)
DELAY
LINE
DELAY
LINE
DATA
ASSEMBLER
I
LATCH
P2D(15:0)
Q
LATCH
CLOCK GENERATION/DISTRIBUTION
2× 2× 2×
n × fDAC/8
n = 0, 1, 2 ... 7
2× 2× 2×
DIGITAL CONTROLLER
SERIAL
PERIPHERAL
INTERFACE
POWER-ON
RESET
Figure 2. Functional Block Diagram
AD9776/AD9778/AD9779
CLOCK
MULTIPLIER
2×/4×/8×
SYNC1
16-BIT
IDAC
CLK+
CLK–
IOUT1_P
IOUT1_N
SYNC1
10
GAIN
10
GAIN
10
GAIN
10
GAIN
16-BIT
QDAC
IOUT2_P
IOUT2_N
VREF
I120
AUX1_P
AUX1_N
AUX2_P
AUX2_N
Rev. A | Page 3 of 56










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