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PDF 74LS375 Data sheet ( Hoja de datos )

Número de pieza 74LS375
Descripción 4-BIT D LATCH
Fabricantes Motorola Semiconductors 
Logotipo Motorola Semiconductors Logotipo



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No Preview Available ! 74LS375 Hoja de datos, Descripción, Manual

4-BIT D LATCH
The SN54/ 74LS375 is a 4-Bit D-Type Latch for use as temporary storage
for binary information between processing limits and input /output or indicator
units. When the Enable (E) is HIGH, information present at the D input will be
transferred to the Q output and, if E is HIGH, the Q output will follow the input.
When E goes LOW, the information present at the D input prior to its setup time
will be retained at the Q outputs.
VCC
16
CONNECTION DIAGRAM DIP (TOP VIEW)
D3
Q3
Q3
E2,3
Q2
Q2
D2
15
14
13
12
11
10
9
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
1
D0
2
Q0
3
Q0
4
E0,1
5
Q1
6
Q1
7
D1
8
GND
TRUTH TABLE
(Each latch)
tn tn+1
DQ
HH
LL
NOTES:
tn = bit time before enable
negative-going transition.
tn+1 = bit time after enable
negative-going transition.
PIN NAMES
LOADING (Note a)
HIGH
LOW
D1 – D4
Data Inputs
0.5 U.L.
0.25 U.L.
E0 – 1
E2 – 3
Q1 – Q4
Q1 – Q4
Enable Input Latches 0, 1
Enable Input Latches 2, 3
Latch Outputs (Note b)
Complimentary Latch Outputs (Note b)
2.0 U.L.
2.0 U.L.
10 U.L.
10 U.L.
1.0 U.L.
1.0 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 25 U.L. for Military (54) and 5 U.L. for Commercial (74)
Temperature Ranges.
DATA
LOGIC DIAGRAM
ENABLE
TO OTHER LATCH
Q
Q
SN54/74LS375
4-BIT D LATCH
LOW POWER SCHOTTKY
16
1
16
1
16
1
J SUFFIX
CERAMIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ
SN74LSXXXN
SN74LSXXXD
Ceramic
Plastic
SOIC
LOGIC SYMBOL
17
9
15
4
12
E0,1
D0
D1
E2,3
Q0
Q1
D2
Q2
D3
Q3
23
6 5 10 11 14 13
VCC = PIN 16
GND = PIN 8
FAST AND LS TTL DATA
5-528

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74LS375 pdf
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different
applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does
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against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
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Literature Distribution Centers:
USA: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036.
EUROPE: Motorola Ltd.; European Literature Centre; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England.
JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141, Japan.
ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.
FAST AND LS TTL DATA
5-532

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