PDF 2128VL Data sheet ( Hoja de datos )

Número de pieza	2128VL
Descripción	2.5VIn-SystemProgrammableSuperFASTHighDensityPLD
Fabricantes	LatticeSemiconductor
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No Preview Available ! ispLSI® 2128VL 2.5V In-System Programmable SuperFAST™ High Density PLD Features Functional Block Diagram* • SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — 6000 PLD Gates — 128 and 64 I/O Pin Versions, Eight Dedicated Inputs — 128 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic — 100% Functional, JEDEC and Pinout Compatible with ispLSI 2128V and 2128VE Devices • 2.5V LOW VOLTAGE 2128 ARCHITECTURE — Interfaces with Standard 3.3V Devices (Inputs and I/Os are 3.3V Tolerant) — 125 mA Typical Active Current • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 150 MHz Maximum Operating Frequency — tpd = 6.0 ns Propagation Delay — Electrically Erasable and Reprogrammable — Non-Volatile — 100% Tested at Time of Manufacture — Unused Product Term Shutdown Saves Power • IN-SYSTEM PROGRAMMABLE — 2.5V In-System Programmability (ISP™) Using Boundary Scan Test Access Port (TAP) — Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of Wired- OR Bus Arbitration Logic — Increased Manufacturing Yields, Reduced Time-to- Market and Improved Product Quality — Reprogram Soldered Devices for Faster Prototyping • 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE • THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS — Enhanced Pin Locking Capability — Three Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Programmable Output Slew Rate Control — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity • ispDesignEXPERT™ – LOGIC COMPILER AND COM- PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING — Superior Quality of Results — Tightly Integrated with Leading CAE Vendor Tools — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms Output Routing Pool (ORP) D7 D6 D5 D4 Output Routing Pool (ORP) D3 D2 D1 D0 A0 C7 A1 C6 A2 DQ C5 A3 C4 DQ Logic A4 Array DQ GLB C3 A5 C2 DQ A6 C1 A7 Global Routing Pool (GRP) C0 B0 B1 B2 B3 Output Routing Pool (ORP) B4 B5 B6 B7 Output Routing Pool (ORP) *128 I/O version shown 0139A/2128VL Description The ispLSI 2128VL is a High Density Programmable Logic Device available in 128 and 64 I/O-pin versions. The device contains 128 Registers, eight Dedicated Input pins, three Dedicated Clock Input pins, two dedi- cated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2128VL fea- tures in-system programmability through the Boundary Scan Test Access Port (TAP) and is 100% IEEE 1149.1 Boundary Scan Testable. The ispLSI 2128VL offers non- volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 2128VL device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. D7 (see Figure 1). There are a total of 32 GLBs in the ispLSI 2128VL device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com September 2000 2128vL_02 1 1 page Specifications ispLSI 2128VL External Timing Parameters Over Recommended Operating Conditions PARAMETER TEST 3 COND. # DESCRIPTION1 -150 -135 -100 UNITS MIN. MAX. MIN. MAX. MIN. MAX. tpd1 A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass — 6.0 — 7.5 — 10.0 ns tpd2 A 2 Data Propagation Delay — 8.5 — 10.0 — 13.0 ns fmax A 3 Clock Frequency with Internal Feedback 2 150 — 135 — 100 — MHz fmax (Ext.) fmax (Tog.) — 4 Clock Frequency with External Feedback (1 tsu2 + )tco1 111 — 95 — 77 — MHz — 5 Clock Frequency, Max. Toggle 166 — 143 — 100 — MHz tsu1 — 6 GLB Reg. Setup Time before Clock, 4 PT Bypass 4.0 — 5.0 — 6.5 — ns tco1 A 7 GLB Reg. Clock to Output Delay, ORP Bypass — 4.0 — 4.5 — 5.0 ns th1 — 8 GLB Reg. Hold Time after Clock, 4 PT Bypass 0.0 — 0.0 — 0.0 — ns tsu2 — 9 GLB Reg. Setup Time before Clock 5.0 — 6.0 — 8.0 — ns tco2 A 10 GLB Reg. Clock to Output Delay — 5.0 — 5.5 — 6.0 ns th2 — 11 GLB Reg. Hold Time after Clock 0.0 — 0.0 — 0.0 — ns tr1 A 12 Ext. Reset Pin to Output Delay, ORP Bypass — 6.0 — 8.0 — 13.5 ns trw1 — 13 Ext. Reset Pulse Duration 5.0 — 5.5 — 6.5 — ns tptoeen B 14 Input to Output Enable — 10.0 — 12.0 — 15.0 ns tptoedis C 15 Input to Output Disable — 10.0 — 12.0 — 15.0 ns tgoeen B 16 Global OE Output Enable — 6.0 — 7.0 — 9.0 ns tgoedis C 17 Global OE Output Disable — 6.0 — 7.0 — 9.0 ns twh — 18 External Synchronous Clock Pulse Duration, High 3.0 — 3.5 — 5.0 — ns twl — 19 External Synchronous Clock Pulse Duration, Low 3.0 — 3.5 — 5.0 — ns 1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock. 2. Standard 16-bit counter using GRP feedback. 3. Reference Switching Test Conditions section. Table 2-0030/2128VL 5 5 Page Specifications ispLSI 2128VL I/O Locations Signal I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 I/O 33 I/O 34 I/O 35 I/O 36 I/O 37 I/O 38 I/O 39 I/O 40 I/O 41 I/O 42 I/O 43 I/O 44 I/O 45 I/O 46 I/O 47 I/O 48 I/O 49 I/O 50 I/O 51 I/O 52 I/O 53 I/O 54 I/O 55 I/O 56 I/O 57 I/O 58 I/O 59 I/O 60 I/O 61 I/O 62 I/O 63 208 fpBGA J2 J4 K1 K3 K2 K4 L1 L2 L3 M1 M2 M3 N1 N2 N3 P4 T3 R4 T4 P5 R5 N6 T5 R6 P6 T6 N7 R7 P7 T7 N8 R8 T9 P9 R9 N9 T10 P10 R10 N10 T11 P11 R11 T12 P12 R12 T13 R13 T14 N14 P16 N15 N16 M14 M15 M16 L15 L14 L16 K13 K15 K14 K16 J13 176 TQFP 28 29 30 31 32 33 34 35 37 38 39 40 41 42 44 45 47 48 49 50 51 52 53 54 56 57 58 59 60 61 62 63 70 71 72 73 74 75 76 77 79 80 81 82 83 84 85 86 88 89 91 92 93 94 95 96 98 99 100 101 102 103 104 105 160 PQFP 25 26 27 28 29 30 31 32 33 34 35 36 37 38 40 41 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 80 81 83 84 85 86 87 88 89 90 91 92 93 94 95 96 100 caBGA G1 F3 E4 H1 G2 J1 H2 K1 J2 K2 H3 J3 G4 H4 K4 H5 F5 J6 K7 H6 K8 G6 J7 K9 J8 K10 J9 J10 H9 H10 G7 G8 D10 E8 F7 C10 D9 B10 C9 A10 B9 A9 C8 B8 D7 C7 A7 C6 E6 B5 A4 C5 A3 D5 B4 A2 B3 A1 B2 B1 C2 C1 D4 D3 100 TQFP 17 18 19 20 22 23 24 26 27 28 29 30 32 33 34 35 40 41 42 43 45 46 47 48 49 51 52 53 55 56 57 58 67 68 69 70 72 73 74 76 77 78 79 80 82 83 84 85 90 91 92 93 95 96 97 98 99 1 2 3 5 6 7 8 Signal I/O 64 I/O 65 I/O 66 I/O 67 I/O 68 I/O 69 I/O 70 I/O 71 I/O 72 I/O 73 I/O 74 I/O 75 I/O 76 I/O 77 I/O 78 I/O 79 I/O 80 I/O 81 I/O 82 I/O 83 I/O 84 I/O 85 I/O 86 I/O 87 I/O 88 I/O 89 I/O 90 I/O 91 I/O 92 I/O 93 I/O 94 I/O 95 I/O 96 I/O 97 I/O 98 I/O 99 I/O 100 I/O 101 I/O 102 I/O 103 I/O 104 I/O 105 I/O 106 I/O 107 I/O 108 I/O 109 I/O 110 I/O 111 I/O 112 I/O 113 I/O 114 I/O 115 I/O 116 I/O 117 I/O 118 I/O 119 I/O 120 I/O 121 I/O 122 I/O 123 I/O 124 I/O 125 I/O 126 I/O 127 208 fpBGA H15 H13 G16 G14 G15 G13 F16 F14 F15 E16 E14 E15 D16 C16 D15 A14 C13 B13 A13 C12 B12 D11 A12 C11 B11 D10 A11 B10 C10 D9 A10 B9 A8 C8 B8 D8 A7 C7 B7 D7 A6 C6 B6 A5 C5 B5 A4 B4 C4 A1 C1 D3 D2 D1 E3 E2 E1 F3 F2 F1 G4 G2 G3 G1 176 TQFP 116 117 118 119 120 121 122 123 125 126 127 128 129 130 132 133 135 136 137 138 139 140 141 142 144 145 146 147 148 149 150 151 158 159 160 161 162 163 164 165 167 168 169 170 171 172 173 174 176 1 3 4 5 6 7 8 10 11 12 13 14 15 16 17 160 PQFP 105 106 107 108 109 110 111 112 113 114 115 116 117 118 120 121 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 160 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 100 caBGA — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 100 TQFP — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 11 11 Page

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