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2128E PDF даташит

Спецификация 2128E изготовлена ​​​​«LatticeSemiconductor» и имеет функцию, называемую «In-SystemProgrammableSuperFASTHighDensityPLD».

Детали детали

Номер произв 2128E
Описание In-SystemProgrammableSuperFASTHighDensityPLD
Производители LatticeSemiconductor
логотип LatticeSemiconductor логотип 

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2128E Даташит, Описание, Даташиты
ispLSI® 2128E
In-System Programmable
SuperFAST™ High Density PLD
Features
Functional Block Diagram
• SUPERFAST HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
Output Routing Pool (ORP)
Output Routing Pool (ORP)
— 6000 PLD Gates
D7 D6 D5 D4 D3 D2 D1 D0
— 128 I/O Pins, Eight Dedicated Inputs
A0
C7
— 128 Registers
— High Speed Global Interconnect
A1
C6
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
A2
DQ
C5
— Small Logic Block Size for Random Logic
— 100% Functional/JEDEC Upward Compatible with
ispLSI 2128 Devices
A3
A4
Logic
Array
DQ
DQ
GLB
C4
C3
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
fmax = 180 MHz Maximum Operating Frequency
tpd = 5.0 ns Propagation Delay
A5
A6
DQ
C2
C1
— TTL Compatible Inputs and Outputs
— 5V Programmable Logic Core
A7 Global Routing Pool (GRP) C0
— ispJTAG™ In-System Programmable via IEEE 1149.1
B0 B1 B2 B3 B4 B5 B6 B7
(JTAG) Test Access Port
— User-Selectable 3.3V or 5V I/O Supports Mixed-
Output Routing Pool (ORP)
Output Routing Pool (ORP)
Voltage Systems
0139(9A)/2128
— PCI Compatible Outputs
— Open-Drain Output Option
Description
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Unused Product Term Shutdown Saves Power
The ispLSI 2128E is a High Density Programmable Logic
Device. The device contains 128 Registers, 128 Univer-
• ispLSI OFFERS THE FOLLOWING ADDED FEATURES
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
sal I/O pins, eight Dedicated Input pins, three Dedicated
Clock Input pins, two dedicated Global OE input pins and
a Global Routing Pool (GRP). The GRP provides com-
plete interconnectivity between all of these elements.
The ispLSI 2128E features 5V in-system programmabil-
ity and in-system diagnostic capabilities. The ispLSI
2128E offers non-volatile reprogrammability of all logic,
as well as the interconnect to provide truly reconfigurable
systems.
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
The basic unit of logic on the ispLSI 2128E device is the
Generic Logic Block (GLB). The GLBs are labeled A0, A1
.. D7 (see Figure 1). There are a total of 32 GLBs in the
ispLSI 2128E device. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or
registered.Inputs to the GLB come from the GRP and
dedicated inputs. All of the GLB outputs are brought back
into the GRP so that they can be connected to the inputs
— Superior Quality of Results
of any GLB on the device.
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
The device also has 128 I/O cells, each of which is
Tools, Timing Simulator and ispANALYZER™
directly connected to an I/O pin. Each I/O cell can be
— PC and UNIX Platforms
Copyright © 1998 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
November 1998
2128e_02
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2128E Даташит, Описание, Даташиты
Specifications ispLSI 2128E
Functional Block Diagram
Figure 1. ispLSI 2128E Functional Block Diagram
RESET
GOE 0
GOE 1
Megablock
Generic Logic
Blocks (GLBs)
Output Routing Pool (ORP)
Input Bus
Output Routing Pool (ORP)
D7 D6 D5 D4 D3 D2 D1 D0
C7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
I/O 31
TCK/ IN 0
TMS/IN 1
BSCAN
A0
A1
A2
Global
Routing
A3
Pool
(GRP)
A4
A5
A6
A7
B0 B1 B2 B3 B4 B5 B6 B7
Output Routing Pool (ORP)
Input Bus
Output Routing Pool (ORP)
C6
C5
C4
C3
C2
C1
C0
IN 5
IN 4
I/O 95
I/O 94
I/O 93
I/O 92
I/O 91
I/O 90
I/O 89
I/O 88
I/O 87
I/O 86
I/O 85
I/O 84
I/O 83
I/O 82
I/O 81
I/O 80
I/O 79
I/O 78
I/O 77
I/O 76
I/O 75
I/O 74
I/O 73
I/O 72
I/O 71
I/O 70
I/O 69
I/O 68
I/O 67
I/O 66
I/O 65
I/O 64
0139/2128E
individually programmed to be a combinatorial input,
output or bi-directional I/O pin with 3-state control. The
signal levels are TTL compatible voltages and the output
drivers can source 4 mA or sink 8 mA. Each output can
be programmed independently for fast or slow output
slew rate to minimize overall output switching noise. By
connecting the VCCIO pins to a common 5V or 3.3V
power supply, I/O output levels can be matched to 5V or
3.3V compatible voltages. When connected to a 5V
supply, the I/O pins provide PCI-compatible output drive.
Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock (see
Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by the two ORPs. Each
ispLSI 2128E device contains four Megablocks.
The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2128E device are selected using the
dedicated clock pins. Three dedicated clock pins (Y0, Y1,
Y2) or an asynchronous clock can be selected on a GLB
basis. The asynchronous or Product Term clock can be
generated in any GLB for its own clock.
Programmable Open-Drain Outputs
In addition to the standard output configuration, the
outputs of the ispLSI 2128E are individually program-
mable, either as a standard totem-pole output or an
open-drain output. The totem-pole output drives the
specified Voh and Vol levels, whereas the open-drain
output drives only the specified Vol. The Voh level on the
open-drain output depends on the external loading and
pull-up. This output configuration is controlled by a pro-
grammable fuse. The default configuration when the
device is in bulk erased state is totem-pole configuration.
The open-drain/totem-pole option is selectable through
the ispDesignEXPERT software tools.
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2128E Даташит, Описание, Даташиты
Specifications ispLSI 2128E
Absolute Maximum Ratings 1
Supply Voltage Vcc .................................. -0.5 to +7.0V
Input Voltage Applied ........................ -2.5 to VCC +1.0V
Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V
Storage Temperature ................................ -65 to 150°C
Case Temp. with Power Applied .............. -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ... 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
SYMBOL
VCC
VCCIO
VIL
VIH
PARAMETER
Supply Voltage: Logic Core, Input Buffers
5V
Supply Voltage: Output Drivers
3.3V
Input Low Voltage
Input High Voltage
Capacitance (TA=25°C, f=1.0 MHz)
SYMBOL
C1
C2
C3
PARAMETER
Dedicated Input Capacitance
I/O Capacitance
Clock Capacitance
Erase/Reprogram Specification
TA = 0°C to +70°C
MIN.
4.75
4.75
3.0
0
2.0
MAX. UNITS
5.25 V
5.25 V
3.6 V
0.8 V
Vcc+1
V
Table 2-0005/2128E
TYP
8
8
10
UNITS
pf
pf
pf
TEST CONDITIONS
VCC = 5.0V, VIN = 2.0V
VCC = 5.0V, VI/O = 2.0V
VCC = 5.0V, VY = 2.0V
Table 2-0006/2128E
PARAMETER
Erase/Reprogram Cycles
MINIMUM
10,000
MAXIMUM
UNITS
Cycles
Table 2-0008/2128E
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