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21054E PDF даташит

Спецификация 21054E изготовлена ​​​​«MicrochipTechnology» и имеет функцию, называемую «16K1.8VI2CSERIALEEPROM».

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Номер произв 21054E
Описание 16K1.8VI2CSERIALEEPROM
Производители MicrochipTechnology
логотип MicrochipTechnology логотип 

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21054E Даташит, Описание, Даташиты
24AA16
16K 1.8V I2CSerial EEPROM
FEATURES
• Single supply with operation down to 1.8V
• Low power CMOS technology
- 1 mA active current typical
- 10 µA standby current typical at 5.5V
- 3 µA standby current typical at 1.8V
• Organized as 8 blocks of 256 bytes (8 x 256 x 8)
• 2-wire serial interface bus, I2Ccompatible
• Schmitt trigger, filtered inputs for noise suppres-
sion
• Output slope control to eliminate ground bounce
• 100 kHz (1.8V) and 400 kHz (5V) compatibility
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 16 bytes
• 2 ms typical write cycle time for page-write
• Hardware write protect for entire memory
• Can be operated as a serial ROM
• ESD protection > 4,000V
• 10,000,000 erase/write cycles guaranteed
• Data retention > 200 years
• 8-pin DIP, 8-lead or 14-lead SOIC packages
• Available for extended temperature ranges
- Commercial (C):
- Industrial (I):
0˚C to +70°C
-40°C to +85°C
DESCRIPTION
The Microchip Technology Inc. 24AA16 is a 1.8 volt 16K
bit Electrically Erasable PROM. The device is orga-
nized as eight blocks of 256 x 8-bit memory with a 2-
wire serial interface. Low voltage design permits oper-
ation down to 1.8 volts with standby and active currents
of only 3 µA and 1 mA, respectively. The 24AA16 also
has a page-write capability for up to 16 bytes of data.
The 24AA16 is available in the standard 8-pin DIP and
both 8-lead and 14-lead surface mount SOIC pack-
ages.
I2C is a trademark of Philips Corporation.
PACKAGE TYPES
PDIP
A0 1
A1 2
A2 3
VSS 4
8 VCC
7 WP
6 SCL
5 SDA
8-lead
SOIC
A0
A1
1
2
A2 3
VSS 4
14-lead SOIC
NC 1
A0 2
A1 3
NC 4
A2 5
VSS
6
NC 7
BLOCK DIAGRAM
WP
8 VCC
7 WP
6 SCL
5 SDA
14 NC
13 VCC
12 WP
11 NC
10 SCL
9 SDA
8 NC
HV GENERATOR
I/O
CONTROL
LOGIC
MEMORY
CONTROL
LOGIC
XDEC
SDA SCL
EEPROM
ARRAY
PAGE LATCHES
YDEC
VCC SENSE AMP
VSS R/W CONTROL
© 1996 Microchip Technology Inc.
DS21054E-page 1
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21054E Даташит, Описание, Даташиты
24AA16
1.0 ELECTRICAL CHARACTERISTICS
1.1 Maximum Ratings*
VCC...................................................................................7.0V
All inputs and outputs w.r.t. VSS ................. -0.6V to VCC +1.0V
Storage temperature ..................................... -65˚C to +150˚C
Ambient temp. with power applied ................ -65˚C to +125˚C
Soldering temperature of leads (10 seconds) ............. +300˚C
ESD protection on all pins ..................................................≥ 4 kV
*Notice: Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability
TABLE 1-1: PIN FUNCTION TABLE
Name
VSS
SDA
SCL
WP
VCC
A0, A1, A2
Function
Ground
Serial Address/Data I/O
Serial Clock
Write Protect Input
+1.8V to 5.5V Power Supply
No Internal Connection
TABLE 1-2: DC CHARACTERISTICS
VCC = 1.8V to +5.5V
Commercial (C): Tamb = 0˚C to +70˚C
Industrial (I): Tamb = -40°C to +85°C
Parameter
Symbol Min Typ Max Units
Conditions
WP, SCL and SDA pins:
High level input voltage
VIH .7 VCC
—V
Low level input voltage
VIL
.3 VCC V
Hysteresis of Schmitt trigger inputs VHYS .05 VCC
— V (Note)
Low level output voltage
VOL
.40 V IOL = 3.0 mA, VCC = 1.8V
Input leakage current
ILI -10
10 µA VIN = .1V to VCC
Output leakage current
ILO -10
10 µA VOUT = .1V to VCC
Pin capacitance
(all inputs/outputs
CIN,
COUT
10 pF VCC = 5.0V (Note 1)
Tamb = 25˚C, FCLK = 1 MHz
Operating current
ICC Write — — 3 mA VCC = 5.5V, SCL = 400 kHz
— 0.5 — mA VCC = 1.8V, SCL = 100 kHz
ICC Read — — 1 mA VCC = 5.5V, SCL = 400 kHz
— 0.05 — mA VCC = 1.8V, SCL = 100 kHz
Standby current
ICCS — — 100 µA VCC = 5.5V, SDA=SCL=VCC
— — 30 µA VCC = 3.0V, SDA=SCL=VCC
— 3 — µA VCC = 1.8V, SDA=SCL=VCC
Note: This parameter is periodically sampled and not 100% tested.
FIGURE 1-1: BUS TIMING START/STOP
VHYS
SCL
SDA
TSU:STA
THD:STA
TSU:STO
START
STOP
DS21054E-page 2
© 1996 Microchip Technology Inc.









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21054E Даташит, Описание, Даташиты
24AA16
TABLE 1-3: AC CHARACTERISTICS
Parameter
Symbol
STANDARD
MODE
VCC = 4.5-5.5V
FAST MODE
Units
Remarks
Min Max Min Max
Clock frequency
FCLK
— 100
— 400 kHz
Clock high time
THIGH
4000
600 — ns
Clock low time
TLOW
4700
1300
— ns
SDA and SCL rise time
TR
— 1000 — 300 ns (Note 1)
SDA and SCL fall time TF — 300 — 300 ns (Note 1)
START condition hold
THD:STA 4000
600
— ns After this period the first
time clock pulse is generated
START condition setup TSU:STA 4700
600
— ns Only relevant for repeated
time START condition
Data input hold time
THD:DAT
0
0 — ns
Data input setup time
TSU:DAT
250
100 — ns
STOP condition setup
TSU:STO 4000
600
— ns
time
Output valid from clock
TAA
— 3500 — 900 ns (Note 2)
Bus free time
TBUF
4700
1300
— ns Time the bus must be free
before a new transmission
can start
Output fall time from VIH
min to VIL max
TOF
250 20 +0.1 250
ns (Note 1), CB 100 pF
CB
Input filter spike suppres- TSP — 50 — 50 ns (Note 3)
sion (SDA and SCL pins)
Write cycle time
TWR — 10 — 10 ms Byte or Page mode
Endurance
— 10M — 10M — cycles 25°C, Vcc = 5.0V, Block
Mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions
3: The combined TSP and VHYS =specifications are due to new Schmitt trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.
FIGURE 1-2: BUS TIMING DATA
TF
TLOW
THIGH
TR
SCL
TSU:STA
SDA
IN
TSP
TAA
THD:STA
THD:DAT
THD:STA
TAA
TSU:DAT
TSU:STO
TBUF
SDA
OUT
© 1996 Microchip Technology Inc.
DS21054E-page 3










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