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PDF PIC12CE674 Data sheet ( Hoja de datos )
| Número de pieza | PIC12CE674 | |
| Descripción | 8-Bit CMOS Microcontroller | |
| Fabricantes | Microchip | |
| Logotipo |  |
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M
PIC12CE67X
8-Pin, 8-Bit CMOS Microcontroller with A/D Converter
and EEPROM Data Memory
Devices Included in this Data Sheet:
• PIC12CE673
• PIC12CE674
High-Performance RISC CPU:
• Only 35 single word instructions to learn
• All instructions are single cycle (400 ns) except for
program branches which are two-cycle
• Operating speed: DC - 10 MHz clock input
DC - 400 ns instruction cycle
Device
Program
Memory
Data
RAM
Data
EEPROM
PIC12CE673 1024 x 14 128 x 8
16 x 8
PIC12CE674 2048 x 14 128 x 8
16 x 8
• 14-bit wide instructions
• 8-bit wide data path
• Interrupt capability
• Special function hardware registers
• 8-level deep hardware stack
• Direct, indirect and relative addressing modes for
data and instructions
Peripheral Features:
• Four-channel, 8-bit A/D converter
• 8-bit real time clock/counter (TMR0) with 8-bit
programmable prescaler
• Interrupt on pin change (GP0, GP1, GP3)
• 1,000,000 erase/write cycle EEPROM data
memory
• EEPROM data retention > 40 years
Pin Diagram:
PDIP, Windowed CERDIP
VDD
GP5/OSC1/CLKIN
GP4/OSC2/AN3/CLKOUT
GP3/MCLR/VPP
18
27
36
45
VSS
GP0/AN0
GP1/AN1/VREF
GP2/T0CKI/AN2/INT
Special Microcontroller Features:
• In-Circuit Serial Programming (ICSP™)
• Internal 4 MHz oscillator with programmable
calibration
• Selectable clockout
• Power-on Reset (POR)
• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Programmable code protection
• Power saving SLEEP mode
• Internal pull-ups on I/O pins (GP0, GP1, GP3)
• Internal pull-up on MCLR pin
• Selectable oscillator options:
- INTRC: Precision internal 4 MHz oscillator
- EXTRC: External low-cost RC oscillator
- XT: Standard crystal/resonator
- HS: High speed crystal/resonator
- LP: Power saving, low frequency crystal
CMOS Technology:
• Low-power, high-speed CMOS EPROM/
EEPROM technology
• Fully static design
• Wide operating voltage range 2.5V to 5.5V
• Commercial, Industrial, and Extended
temperature ranges
• Low power consumption
< 2 mA @ 5V, 4 MHz
15 µA typical @ 3V, 32 kHz
< 1 µA typical standby current
© 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 1
http://www.Datasheet4U.com/
1 page  
2.0 PIC12CE67X DEVICE
VARIETIES
A variety of frequency r anges and pac kaging options
are available. Depending on application and production
requirements, the proper device option can be selected
using the information in thePIC12CE67X Product Iden-
tification System section at the end of this data sheet.
When placing orders, please use that page of the data
sheet to specify the correct part number.
For example, the PIC12C E67X d evice “type” is indi-
cated in the device number:
1. CE, as in PIC12 CE674. These de vices ha ve
OTP program memory, EEPROM data memory
and operate over the standard voltage range.
2.1 UV Erasable Devices
The UV er asable v ersion, off ered in windowed pac k-
age, is optimal for prototype development and pilot pro-
grams.
The UV er asable v ersion can be er ased and repro-
grammed to an y of the confi guration modes .
Microchip's PICSTART® P lus a nd PR O MATE® pro-
grammers both suppor t the PIC1 2CE67X. Third par ty
programmers also are available; refer to the Microchip
Third Party Guide for a list of sources.
Note:
Please note that er asing the de vice will
also er ase the pre- programmed inter nal
calibration value for the inter nal oscillator.
The calibration value must be sa ved prior
to erasing the part.
2.2 One-Time-Programmable (OTP)
Devices
The availability of OTP devices is especially useful for
customers who need the fl exibility f or frequent code
updates and small volume applications.
The OTP devices, packaged in plasti c packages, per-
mit the user to prog ram them once . In addition to the
program memor y, the confi guration bits m ust also be
programmed.
PIC12CE67X
2.3 Quick-Turn-Programming (QTP)
Devices
Microchip offers a QTP Programming Ser vice for fac-
tory production orders . This ser vice is made a vailable
for users who choose not to program a medium to high
quantity of units and whose code patter ns have stabi-
lized. The devices are identical to the OTP devices but
with all EPR OM locations and configuration o ptions
already programmed by the f actory. Cer tain code and
prototype verification procedures apply before produc-
tion shipments are available. Please contact your local
Microchip Technology sales office for more details.
2.4 Serialized Quick-Turn Programming
(SQTPSM) Devices
Microchip offers a unique programming service where
a f ew user-defi ned locations in each de vice are pro-
grammed with different serial numbers. The serial num-
bers may be random, pseudo-random, or sequential.
Serial prog ramming allo ws each de vice to ha ve a
unique n umber which can ser ve as an entr y-code,
password, or ID number.
© 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 5
http://www.Datasheet4U.com/
5 Page 
4.0 MEMORY ORGANIZATION
4.1 Program Memory Organization
The PIC12CE67X has a 13-bit program counter capa-
ble of addressing an 8K x 14 program memory space.
For the PIC12CE673 the first 1K x 14 (0000h-03FFh) is
implemented.
For the PIC12CE674, the first 2K x 14 (0000h-07FFh)
is implemented. Accessing a location above the physi-
cally implemented address will cause a wr aparound.
The reset vector is at 0000h and the interrupt vector is
at 0004h.
FIGURE 4-1: PIC12CE67X PROGRAM
MEMORY MAP AND STACK
PC<12:0>
CALL, RETURN
RETFIE, RETLW
13
Stack Level 1
Stack Level 8
Reset Vector
0000h
PIC12CE67X
4.2 Data Memory Organization
The data memor y is par titioned into tw o Banks which
contain the General Purpose Registers and theSpecial
Function Registers. Bit RP0 is the bank select bit.
RP0 (STATUS<5>) = 1 → Bank 1
RP0 (STATUS<5>) = 0 → Bank 0
Each Bank e xtends up to 7Fh (128 b ytes). The lower
locations of each Bank are reser ved f or the Special
Function Registers. Above the Special Function Regis-
ters are Gener al Pur pose Registers implemented as
static RAM. Both Bank 0 and Bank 1 contain special
function registers . Some "high use" special function
registers from Bank 0 are mirrored in Bank 1 f or code
reduction and quicker access.
Also note that F0h through FFh on the PIC12CE67X is
mapped into Bank 0 registers 70h-7Fh as common
RAM.
4.2.1 GENERAL PURPOSE REGISTER FILE
The register file can be accessed either directly, or indi-
rectly through the File Select R egister FSR
(Section 4.5).
Peripheral Interrupt Vector 0004h
0005h
On-chip Program
Memory
(PIC12CE674 only)
03FFh
0400h
07FFh
0800h
1FFFh
© 1998 Microchip Technology Inc.
Preliminary
DS40181B-page 11
http://www.Datasheet4U.com/
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PIC12CE674.PDF ] | |
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