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PDF SPC560B44L3 Data sheet ( Hoja de datos )
| Número de pieza | SPC560B44L3 | |
| Descripción | 32-bit MCU family built on the Power Architecture embedded category | |
| Fabricantes | ST Microelectronics | |
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SPC560B40x, SPC560B44x, SPC560B50x
SPC560C40x, SPC560C44x, SPC560C50x
32-bit MCU family built on the Power Architecture® embedded
category for automotive body electronics applications
Features
■ High-performance 64 MHz e200z0h CPU
– 32-bit Power Architecture® technology
– Up to 60 DMIPs operation
– Variable length encoding (VLE)
■ Memory
– Up to 512 Kbytes Code Flash, with ECC
– 64 Kbytes Data Flash, with ECC
– Up to 48 Kbytes SRAM, with ECC
– 8-entry memory protection unit (MPU)
■ Interrupts
– 16 priority levels
– Non-maskable interrupt (NMI)
– Up to 34 ext. int. including 18 wakeup lines
■ GPIO: QFP64/45, QFP100/75, QFP144/123
■ Timer units
– 6-channel 32-bit periodic interrupt timers
– 4-channel 32-bit system timer module
– System watchdog timer
– Real-time clock timer
■ 16-bit counter time-triggered I/Os
– Up to 56 channels with PWM/MC/IC/OC
– ADC diagnostic via CTU
■ Communications interface
– Up to 6 FlexCAN interfaces (2.0B active)
with 64-message objects each
– Up to 4 LINFlex/UART
– 3 DSPI / I2C
Table 1. Device summary
LQFP100 (14 x 14 x 1.4 mm)
LQFP144 (20 x 20 x 1.4 mm)
LQFP64 (10 x 10 x 1.4 mm)
■ 10-bit A/D converter with up to 36 channels
– Up to 64 channels via external multiplexing
– Individual conversion registers
– Cross triggering unit
■ Dedicated diagnostic module for lighting
– Advanced PWM generation
– Time-triggered diagnostic
– PWM-synchronized ADC measurements
■ Clock generation
– 4 to 16 MHz fast external crystal oscillator
– 32 KHz slow external crystal oscillator
– 16 MHz fast internal RC oscillator
– 128 kHz slow internal RC oscillator
– Software-controlled FMPLL
– Clock monitoring unit
■ Exhaustive debugging capability
– Nexus1 on all devices
– Nexus2+ available on emulation package
■ Low power capabilities
– Ultra-low power standby with RTC, SRAM
and CAN monitoring
– Fast wakeup schemes
■ Operating temp. range up to -40 to 125 °C
■ Single 5 V or 3.3 V supply
Package
256 Kbyte code Flash
384 Kbyte code Flash
512 Kbyte code Flash
LQFP144 SPC560B40L5 — SPC560B44L5 — SPC560B50L5 —
LQFP100 SPC560B40L3 SPC560C40L3 SPC560B44L3 SPC560C44L3 SPC560B50L3 SPC560C50L3
LQFP64
SPC560B40L1 SPC560C40L1
LBGA208(1)
—
—
—
—
— SPC560B50L1 SPC560C50L1
— SPC560B50B2 —
1. LBGA208 available only as development package for Nexus2+
July 2010
Doc ID 14619 Rev 7
1/113
www.st.com
1
1 page  
SPC560Bx, SPC560Cx
www.DataSheet4U.com
List of tables
Table 49.
Table 50.
Table 51.
Table 52.
LBGA208 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Order Codes for Engineering Samples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Doc ID 14619 Rev 7
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SPC560Bx, SPC560Cx
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Block diagram
Table 3 summarizes the functions of all blocks present in the SPC560Bx and SPC560Cx
series of microcontrollers. Please note that the presence and number of blocks varies by
device and package.
Table 3.
SPC560Bx and SPC560Cx series block summary
Block
Function
Analog-to-digital converter (ADC) Multi-channel, 10-bit analog-to digital-converter
Boot assist module (BAM)
A block of read-only memory containing VLE code which is executed according
to the boot mode of the device
Clock monitor unit (CMU)
Monitors clock source (internal and external) integrity
Cross triggering unit (CTU)
Enables synchronization of ADC conversions with a timer event from the eMIOS
or from the PIT
Deserial serial peripheral
interface (DSPI)
Provides a synchronous serial interface for communication with external
devices
Error Correction Status Module
(ECSM)
Provides a myriad of miscellaneous control functions for the device including
program-visible information about configuration and revision levels, a reset
status register, wakeup control for exiting sleep modes, and optional features
such as information on memory errors reported by error-correcting codes
Enhanced Direct Memory Access Performs complex data transfers with minimal intervention from a host
(eDMA)
processor via “n” programmable channels.
Enhanced modular input output
system (eMIOS)
Provides the functionality to generate or measure events
Flash memory
Provides non-volatile storage for program code, constants and variables
FlexCAN (controller area
network)
Supports the standard CAN communications protocol
FMPLL (frequency-modulated
phase-locked loop)
Generates high-speed system clocks and supports programmable frequency
modulation
Internal multiplexer (IMUX) SIU
subblock
Allows flexible mapping of peripheral interface on the different pins of the device
Inter-integrated circuit (I2C™) bus
A two wire bidirectional serial bus that provides a simple and efficient method of
data exchange between devices
Interrupt controller (INTC)
Provides priority-based preemptive scheduling of interrupt requests
JTAG controller
Provides the means to test chip functionality and connectivity while remaining
transparent to system logic when not in test mode
LINflex controller
Manages a high number of LIN (Local Interconnect Network protocol)
messages efficiently with a minimum of CPU load
Clock generation module
(MC_CGM)
Provides logic and control required for the generation of system and peripheral
clocks
Mode entry module (MC_ME)
Provides a mechanism for controlling the device operational mode and mode
transition sequences in all functional states; also manages the power control
unit, reset generation module and clock generation module, and holds the
configuration, control and status registers accessible for applications
Power control unit (MC_PCU)
Reduces the overall power consumption by disconnecting parts of the device
from the power supply via a power switching device; device components are
grouped into sections called “power domains” which are controlled by the PCU
Doc ID 14619 Rev 7
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| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet SPC560B44L3.PDF ] | |
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