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DM9374 PDF даташит

Спецификация DM9374 изготовлена ​​​​«Fairchild Semiconductor» и имеет функцию, называемую «7-Segment Decoder/Driver/Latch».

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Номер произв DM9374
Описание 7-Segment Decoder/Driver/Latch
Производители Fairchild Semiconductor
логотип Fairchild Semiconductor логотип 

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DM9374 Даташит, Описание, Даташиты
March 1989
Revised March 2000
DM9374
7-Segment Decoder/Driver/Latch
with Constant Current Sink Outputs
General Description
The DM74 is a 7-segment decoder driver incorporating
input latches and output circuits to directly drive common
anode LED displays.
Ordering Code:
Order Number Package Number
Package Description
DM9374N
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Connection Diagram
Logic Symbol
Pin Descriptions
VCC = Pin 16
GND = Pin 8
Pin
Names
A0–A3
LE
RBI
RBO
a –g
Description
Address (Data Inputs)
Latch Enable Input (Active LOW)
Ripple Blanking Input (Active LOW)
Ripple Blanking as Output (Active LOW)
as Input (Active LOW)
Constant Current Outputs (Active LOW)
© 2000 Fairchild Semiconductor Corporation DS010210
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DM9374 Даташит, Описание, Даташиты
Truth Table
Binary
State
0
0
1
LE
H
L
L
L
Inputs
Outputs
RBI
(Note 1)
L
H
X
A3 A2 A1 A0 a b c d e f g
XXXX
STABLE
L L L L HHHHHHH
L L L L LLLLLLH
L L L H HL LHHHH
RBO
H
L
H
H
Display
Stable
Blank
0
1
2L
X
L L H L L LHL LHL
H
3L
X
L L H H L L L LHHL
H
4L
X
L H L L HL LHHL L
H
5L
X
L H L H LHLLHLL
H
2
3
4
5
6L
X
L H H L LHLLLLL
H
7L
X
L H H H L L LHHHH
H
8L
X
H L L L LLLLLLL
H
9L
X
H L L H LLLLHLL
H
10 L
X
H L H L HHHHHHL
H
6
7
8
9
11 L
X
H L H H LHHL L L L
H
12 L
X
H H L L HLLHLLL
H
13 L
X
H H L H HHHL L LH
H
14 L
X
H H H L L LHHL L L
H
15 L
X
H H H H HHHHHHH
H
X X X X X X X H H H H H H H L (Note 2)
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Note 1: The RBI will blank the display only if a binary zero is stored in the latches.
Note 2: RBO used as an input overrides all other input conditions.
E
H
L
P
BLANK
BLANK
Numerical Designations
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DM9374 Даташит, Описание, Даташиты
Functional Description
The DM9374 is a 7-segment decoder/driver with latches on
the address inputs and active LOW constant current out-
puts to drive LEDs directly. This device accepts a 4-bit
binary code and produces output drive to the appropriate
segments of the 7-segment display. It has a decode format
which produces numeric codes “0” through “9” and other
codes.
Latches on the four data inputs are controlled by an active
LOW Latch Enable, LE. When LE is LOW, the state of the
outputs is determined by the input data. When LE goes
HIGH, the last data present at the inputs is stored in the
latches and the outputs remain stable. The LE pulse width
necessary to accept and store data is typically 50 ns, which
allows data to be strobed into the DM9374 at normal TTL
speeds. This feature means that data can be routed
directly from high speed counters and frequency dividers
into the display without slowing down the system clock or
providing intermediate data storage.
The latch/decoder combination is a simple system which
drives LED displays with multiplexed data inputs from MOS
time clocks, DVMs, calculator chips, etc. Data inputs are
multiplexed while the displays are in static mode. This low-
ers component and insertion costs, since several circuits—
seven resistors per display, strobe drivers, a separate dis-
play voltage source, and clock failure detect circuits—tradi-
tionally found in multiplexed display systems are
Logic Diagram
eliminated. It also allows low strobing rates to be used with-
out display flicker.
Another DM9374 feature is the reduced loading on the
data inputs when the Latch Enable is HIGH (only 10 µA
typ). This allows many DM9374s to be driven from a MOS
device in multiplex mode without the need for drivers on
the data lines. The DM9374 also provides automatic blank-
ing of the leading and/or trailing-edge zeroes in a multidigit
decimal number, resulting in an easily readable decimal
display conforming to normal writing practice. In an 8-digit
mixed integer fraction decimal representation, using the
automatic blanking capability 0060.0300 would be dis-
played as 60.03. Leading-edge zero suppression is
obtained by connecting the Ripple Blanking Output (RBO)
of a decoder to the Ripple Blanking Input (RBI) of the next
lower stage device. The most significant decoder stage
should have the RIB input grounded; and since suppres-
sion of the least significant integer zero in a number is not
usually desired, the RBI input of this decoder stage should
be left open. A similar procedure for the fractional part of a
display will provide automatic suppression of trailing-edge
zeroes. The RBO terminal of the decoder can be OR-tied
with a modulating signal via an isolating buffer to achieve
duration intensity modulation. A suitable signal can be gen-
erated for this purpose by forming a variable frequency
multivibrator with a cross coupled pair of TTL or DTL gates.
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