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STA559BW PDF даташит

Спецификация STA559BW изготовлена ​​​​«STMicroelectronics» и имеет функцию, называемую «2.1 channel high-efficiency digital audio system».

Детали детали

Номер произв STA559BW
Описание 2.1 channel high-efficiency digital audio system
Производители STMicroelectronics
логотип STMicroelectronics логотип 

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STA559BW Даташит, Описание, Даташиты
STA559BW
5 V, 2 A, 2.1 channel high-efficiency digital audio system
Sound Terminal®
Datasheet - production data
PowerSSO-36
with exposed pad down (EPD)
Features
Wide-range supply voltage, 4.5 V to 16 V
Three power output configurations:
– 2 channels of ternary PWM (2 x 3 W into
4 at 5 V) + PWM output
– 2 channels of ternary PWM (2 x 3 W into
4 at 5 V) + ternary stereo line-out
– 2.1 channels of binary PWM (left, right,
LFE) (2 x 0.7 W + 1 x 3 W into 4 at 5 V)
(2 x 1.4 W + 1 x 6 W into 2 at 5 V)
FFX with 100-dB SNR and dynamic range
Selectable 32- to 192-kHz input sample rates
I²C control with selectable device address
Digital gain/attenuation +48 dB to -80 dB with
0.5-dB/step resolution
Soft volume update
Individual channel and master gain/attenuation
Two independent limiters/compressors
Dynamic range compression or anti-clipping
modes
Audio presets:
– 15 preset crossover filters
– 5 preset anti-clipping modes
– Preset night-time listening mode
Individual channel soft/hard mute
Independent channel volume and DSP bypass
2-channel I²S input data interface
Input and output channel mapping
Automatic invalid-input detect Mute
Automatic zero-detect mute
Up to 4 user-programmable biquads/channel
Three coefficients banks for EQ presets storing
with fast recall via I²C interface
Bass/treble tones and de-emphasis control
Selectable high-pass filter for DC blocking
Advanced AM interference frequency
switching and noise suppression modes
Selectable high- or low-bandwidth
noise-shaping topologies
Selectable clock input ratio
Thermal overload and short-circuit protection
embedded
Video apps: 576 x fS input mode supported
Table 1. Device summary
Order code
Package
Packaging
STA559BWTR PowerSSO-36 EPD Tape and reel
February 2014
This is information on a product in full production.
DocID18190 Rev 2
1/67
www.st.com
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STA559BW Даташит, Описание, Даташиты
Contents
Contents
STA559BW
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4 Electrical specifications for the digital section . . . . . . . . . . . . . . . . . . . . . 12
3.5 Electrical specifications for the power section . . . . . . . . . . . . . . . . . . . . . 13
3.6 Power on/off sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4 Processing data paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5 I²C bus specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1 Communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1.1 Data transition or change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1.2 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1.3 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1.4 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.2 Device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.3 Write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.3.1 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.3.2 Multi-byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.4 Read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.4.1 Current address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.4.2 Current address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.4.3 Random address byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.4.4 Random address multi-byte read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2/67 DocID18190 Rev 2
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STA559BW Даташит, Описание, Даташиты
STA559BW
Contents
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
Configuration registers (addr 0x00 to 0x05) . . . . . . . . . . . . . . . . . . . . . . . 22
6.1.1 Configuration register A (addr 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.1.2 Configuration register B (addr 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.1.3 Configuration register C (addr 0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1.4 Configuration register D (addr 0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.1.5 Configuration register E (addr 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.1.6 Configuration register F (addr 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Volume control registers (addr 0x06 - 0x0A) . . . . . . . . . . . . . . . . . . . . . . 40
6.2.1 Mute/line output configuration register (addr 0x06) . . . . . . . . . . . . . . . . 41
6.2.2 Master volume register (addr 0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.2.3 Channel 1 volume (addr 0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.2.4 Channel 2 volume (addr 0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.2.5 Channel 3 / line output volume (addr 0x0A) . . . . . . . . . . . . . . . . . . . . . 42
Audio preset registers (addr 0x0B and 0x0C) . . . . . . . . . . . . . . . . . . . . . 43
6.3.1 Audio preset register 1 (addr 0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.3.2 Audio preset register 2 (addr 0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Channel configuration registers (addr 0x0E - 0x10) . . . . . . . . . . . . . . . . . 45
Tone control register (addr 0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Dynamic control registers (addr 0x12 - 0x15) . . . . . . . . . . . . . . . . . . . . . 47
6.6.1 Limiter 1 attack/release rate (addr 0x12) . . . . . . . . . . . . . . . . . . . . . . . . 47
6.6.2 Limiter 1 attack/release threshold (addr 0x13) . . . . . . . . . . . . . . . . . . . 47
6.6.3 Limiter 2 attack/release rate (addr 0x14) . . . . . . . . . . . . . . . . . . . . . . . . 48
6.6.4 Limiter 2 attack/release threshold (addr 0x15) . . . . . . . . . . . . . . . . . . . 48
6.6.5 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
User-defined coefficient control registers (addr 0x16 - 0x26) . . . . . . . . . . 52
6.7.1 Coefficient address register (addr 0x16) . . . . . . . . . . . . . . . . . . . . . . . . 52
6.7.2 Coefficient b1 data register bits (addr 0x17 - 0x19) . . . . . . . . . . . . . . . . 53
6.7.3 Coefficient b2 data register bits (addr 0x1A - 0x1C) . . . . . . . . . . . . . . . 53
6.7.4 Coefficient a1 data register bits (addr 0x1D - 0x1F) . . . . . . . . . . . . . . . 53
6.7.5 Coefficient a2 data register bits (addr 0x20 - 0x22) . . . . . . . . . . . . . . . . 53
6.7.6 Coefficient b0 data register bits (addr 0x23 - 0x25) . . . . . . . . . . . . . . . . 54
6.7.7 Coefficient read/write control register (addr 0x26) . . . . . . . . . . . . . . . . . 54
6.7.8 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Variable max power correction registers (addr 0x27 - 0x28) . . . . . . . . . . 59
Distortion compensation registers (addr 0x29 - 0x2A) . . . . . . . . . . . . . . . 59
Fault detect recovery constant registers (addr 0x2B - 0x2C) . . . . . . . . . . 59
DocID18190 Rev 2
3/67
67
http://www.Datasheet4U.com










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Номер в каталогеОписаниеПроизводители
STA559BW2.1 channel high-efficiency digital audio systemSTMicroelectronics
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