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PDF 74HC595 Data sheet ( Hoja de datos )
| Número de pieza | 74HC595 | |
| Descripción | 8-bit serial-in serial or parallel-out shift register | |
| Fabricantes | NXP Semiconductors | |
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74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output
latches; 3-state
Rev. 8 — 25 February 2016
Product data sheet
1. General description
The 74HC595; 74HCT595 is an 8-bit serial-in/serial or parallel-out shift register with a
storage register and 3-state outputs. Both the shift and storage register have separate
clocks. The device features a serial input (DS) and a serial output (Q7S) to enable
cascading and an asynchronous reset MR input. A LOW on MR will reset the shift register.
Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift
register is transferred to the storage register on a LOW-to-HIGH transition of the STCP
input. If both clocks are connected together, the shift register will always be one clock
pulse ahead of the storage register. Data in the storage register appears at the output
whenever the output enable input (OE) is LOW. A HIGH on OE causes the outputs to
assume a high-impedance OFF-state. Operation of the OE input does not affect the state
of the registers. Inputs include clamp diodes. This enables the use of current limiting
resistors to interface inputs to voltages in excess of VCC.
2. Features and benefits
8-bit serial input
8-bit serial or parallel output
Storage register with 3-state outputs
Shift register with direct clear
100 MHz (typical) shift out frequency
Complies with JEDEC standard no. 7A
Input levels:
For 74HC595: CMOS level
For 74HCT595: TTL level
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
3. Applications
Serial-to-parallel data conversion
Remote control holding register
1 page  
NXP Semiconductors
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
7. Functional description
Table 3. Function table[1]
Control
SHCP STCP OE MR
XXL L
XL L
XXHL
XL H
XL H
LH
Input Output
DS Q7S Qn
X L NC
XL L
XL Z
H Q6S NC
X NC QnS
X Q6S QnS
Function
a LOW-level on MR only affects the shift registers
empty shift register loaded into storage register
shift register clear; parallel outputs in high-impedance OFF-state
logic HIGH-level shifted into shift register stage 0. Contents of all
shift register stages shifted through, e.g. previous state of stage 6
(internal Q6S) appears on the serial output (Q7S).
contents of shift register stages (internal QnS) are transferred to
the storage register and parallel output stages
contents of shift register shifted through; previous contents of the
shift register is transferred to the storage register and the parallel
output stages
[1] H = HIGH voltage state;
L = LOW voltage state;
= LOW-to-HIGH transition;
X = don’t care;
NC = no change;
Z = high-impedance OFF-state.
6+&3
'6
67&3
05
2(
4
4
4
4
46
Fig 7. Timing diagram
=VWDWH
=VWDWH
=VWDWH
=VWDWH
PQD
74HC_HCT595
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 25 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
5 of 23
5 Page 
NXP Semiconductors
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 13.
Symbol Parameter Conditions
25 C
40 C to +85 C 40 C to +125 C Unit
Min Typ[1] Max Min Max Min Max
74HCT595; VCC = 4.5 V to 5.5 V
tpd
propagation SHCP to Q7S; see Figure 8 [2] -
25 42
-
53
-
63 ns
delay
STCP to Qn; see Figure 9
[2] -
24 40
-
50
-
60 ns
MR to Q7S; see Figure 11
[3] -
23 40
-
50
-
60 ns
ten
enable time OE to Qn; see Figure 12
[4] -
21 35
-
44
-
53 ns
tdis
disable time OE to Qn; see Figure 12
[5] -
18 30
-
38
-
45 ns
tW pulse width SHCP HIGH or LOW;
see Figure 8
16 6 - 20 - 24 - ns
STCP HIGH or LOW;
see Figure 9
16 5 - 20 - 24 - ns
MR LOW; see Figure 11
20 8 - 25 - 30 - ns
tsu set-up time DS to SHCP; see Figure 9
SHCP to STCP;
see Figure 10
16 5 - 20 - 24 - ns
16 8 - 20 - 24 - ns
th hold time DS to SHCP; see Figure 10
trec recovery MR to SHCP; see Figure 11
time
3 2 -
3
-
3
10 7 - 13 - 15
- ns
- ns
fmax maximum SHCP and STCP;
frequency see Figure 8 and 9
30 52 - 24 - 20 - MHz
CPD power
fi = 1 MHz;
[6] - 130 -
-
-
-
- pF
dissipation VI = GND to VCC 1.5 V
[7]
capacitance
[1] Typical values are measured at nominal supply voltage.
[2] tpd is the same as tPHL and tPLH.
[3] tpd is the same as tPHL only.
[4] ten is the same as tPZL and tPZH.
[5] tdis is the same as tPLZ and tPHZ.
[6] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
(CL VCC2 fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in V.
[7] All 9 outputs switching.
74HC_HCT595
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 25 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
11 of 23
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet 74HC595.PDF ] | |
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