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AMP374P6453BT1-C1S PDF даташит

Спецификация AMP374P6453BT1-C1S изготовлена ​​​​«AVED» и имеет функцию, называемую «64M X 72 SDRAM DIMM».

Детали детали

Номер произв AMP374P6453BT1-C1S
Описание 64M X 72 SDRAM DIMM
Производители AVED
логотип AVED логотип 

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AMP374P6453BT1-C1S Даташит, Описание, Даташиты
AVED MEMORY PRODUCTS
Where Quality & Memory Merge
AMP374P6453BT1-C1H/S
64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD
DESCRIPTION
AVED Memory Products AMP374P6453BT1-C1H/S is a 64M bit X 72 Synchronous Dynamic RAM high density
memory module. The AVED Memory Products AMP374P6453BT1-C1H/S consists of eighteen CMOS 32M X 8 bit
with 4 banks Synchronous DRAMs in TSOP-II 400mil package and a 2K EEPROM in 8-pin TSSOP package on a
168-pin glass-epoxy substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in
parallel for each SDRAM.
The AVED Memory Products AMP374P6453BT1-C1H/S is a Dual In-Line Memory Module and is intended for mount-
ing into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system
clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies
allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.
APPLICATION
Main Memory unit for computer, Microcomputer memory,
Refresh memory for CRT.
FEATURES
Performance Ranges
Part Identification
- AMP374P6453BT1-C1H/S
8k cycles/64ms Ref, TSOP, Gold Contact Plating
- PC100 Compliant
Part #
Maximum Frequency/Speed
AMP374P6453BT1-C1H/S PC100MHz (10ns @ CL=2)
Burst Mode Operation
Auto & Self Refresh capability (8k cycles/64ms)
LVTTL compatible inputs and outputs
Single 3.3V ± 0.3V power supply
MRS cycle with address key programs
Latency (Access from column address)
Burst Length (1, 2, 4, 8 & Full Page)
Data Scramble (Sequential & Interleave)
All inputs are sampled at the positive
going edge of the system clock
Serial Presence Detect with EEPROM
PIN NAMES
Pin Nam e
A0 - A12
BA0 - BA1
DQ0 - DQ63
CB0 - 7
CLK0 - CLK3
CKE0 - CKE1
CS0 - CS3
RAS
CAS
WE
DQM0 - 7
VDD
Vss
*VREF
SDA
SCL
SA0 - 2
WP
DU
NC
Function
Address Input (multiplexed)
Select Bank
Data Input/Output
Check Bit (Data-in/out)
Clock Input
Clock Enable Input
Chip Select Input
Row Address Strobe
Column Address Strobe
W rite Enable
DQM
Power Supply(3.3V)
G ro u n d
Power Supply for Reference
Serial Address Data I/O
Serial Clock
Address in EEPROM
W rite Protect
Don’t Use
No Connection
Revision: 1.1
Revision Date: 11/2000
Document Number: 65830
Page Number: 1 of 12
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No Preview Available !

AMP374P6453BT1-C1S Даташит, Описание, Даташиты
AVED MEMORY PRODUCTS
Where Quality & Memory Merge
AMP374P6453BT1-C1H/S
64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD
PIN CONFIGURATIONS (FRONT SIDE / BACK SIDE)
Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back
1
Vss
29
DQM1
57 DQ18
85
Vss 113 DQM5 141 DQ50
2
DQ0
30
3
DQ1
31
4
DQ2
32
CS0
58 DQ19 86 DQ32 114
CS1
142 DQ51
DU
59 VDD
87 DQ33 115 RAS
143 VDD
Vss 60 DQ20 88 DQ34 116 Vss 144 DQ52
5
DQ3
33
A0 61 NC 89 DQ35 117 A1 145 NC
6
VDD
34
A2
62 *VREF 90
VDD
118
A3
146 *VREF
7
DQ4
35
A4 63 CKE1 91 DQ36 119 A5 147 NC
8
DQ5
36
A6 64 Vss 92 DQ37 120 A7 148 Vss
9
DQ6
37
A8 65 DQ21 93 DQ38 121 A9 149 DQ53
10 DQ7 38 A10/AP 66 DQ22 94 DQ39 122 BA0 150 DQ54
11 DQ8 39
BA1 67 DQ23 95 DQ40 123 A11 151 DQ55
12 Vss 40 VDD 68 Vss 96 Vss 124 VDD 152 Vss
13 DQ9 41
VDD
69 DQ24 97 DQ41 125 CLK1 153 DQ56
14 DQ10 42
CLK0 70 DQ25 98 DQ42 126 A12 154 DQ57
15 DQ11 43
Vss 71 DQ26 99 DQ43 127 Vss 155 DQ58
16 DQ12 44
DU 72 DQ27 100 DQ44 128 CKE0 156 DQ59
17 DQ13 45 CS2 73 VDD 101 DQ45 129 CS3 157 VDD
18
VDD
46
DQM2 74 DQ28 102
VDD
130 DQM6 158 DQ60
19 DQ14 47 DQM3 75 DQ29 103 DQ46 131 DQM7 159 DQ61
20 DQ15 48
DU 76 DQ30 104 DQ47 132 *A13 160 DQ62
21 CB0 49
VDD
77 DQ31 105 CB4 133 VDD 161 DQ63
22 CB1 50
NC 78 Vss 106 CB5 134 NC 162 Vss
23 Vss 51
NC 79 CLK2 107 Vss 135 NC 163 CLK3
24 NC 52 CB2 80 NC 108 NC 136 CB6 164 NC
25 NC 53 CB3 81 WP 109 NC 137 CB7 165 **SA0
26 VDD 54
Vss 82 **SDA 110 VDD 138 Vss 166 **SA1
27 WE 55
28 DQM0 56
DQ16
DQ17
83 **SCL 111 CAS 139 DQ48 167 **SA2
84 VDD 112 DQM4 140 DQ49 168 VDD
Pins marked * are not used in this module.
Pins marked ** should be NC in the system which does not support SPD.
Revision: 1.1
Revision Date: 11/2000
Document Number: 65830
Page Number: 2 of 12
http://www.Datasheet4U.com









No Preview Available !

AMP374P6453BT1-C1S Даташит, Описание, Даташиты
AVED MEMORY PRODUCTS
Where Quality & Memory Merge
AMP374P6453BT1-C1H/S
64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD
PIN CONFIGURATION DESCRIPTION
Pin Name
CLK
System Clock
CS
CKE
Chip Select
Clock Enable
A0 - A12
BA0 - BA1
RAS
CAS
WE
Address
Bank Select Address
Row Address Strobe
Colum n Address Strobe
W rite Enable
DQM0 - DQM7
DQ0 - DQ63
CB0 - 7
Data Input/Output Mask
Data Input/Output
Check bit
Input Function
Active on the positive going edge to sam ple all inputs.
Disables or enables device operation by masking or enabling all inputs
except CLK, CKE, and DQM.
Masks system clock to freeze operation from the next clock cycle. CKE
should be enabled at least one cycle prior to new comm and. Disable
input buffers for power down in standby.
CKE should be enabled 1CLK+t ss prior to valid com mand.
Row/Column addresses are m ultiplexed on the sam e pins.
Row Address: RA0 RA12, Column address: CA0 CA9
Selects bank to be activated during row address latch tim e.
Selects bank for read/write during column address latch tim e.
Latches row addresses on the positive going edge of the CLK with
RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with
C A S low.
Enables colum n access.
Enables write operation and row precharge.
Latches data in starting from CAS , WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active. (Byte Masking)
Data inputs/outputs are m ultiplexed on the same pins.
Check bits for ECC.
WP
VDD/Vss
W rite Protect
Power Supply/Ground
W P pin is connected to Vss through 47KResistor. W hen W P is high
EEPROM program ming will be inhibited, and the entire m em ory will be
write-protected.
Power and ground for the input buffers and the core logic.
Revision: 1.1
Revision Date: 11/2000
Document Number: 65830
Page Number: 3 of 12
http://www.Datasheet4U.com










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Номер в каталогеОписаниеПроизводители
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