PDF AMP374P6453BT1-C1H Data sheet ( Hoja de datos )

Número de pieza	AMP374P6453BT1-C1H
Descripción	64M X 72 SDRAM DIMM
Fabricantes	AVED
Logotipo
Hay una vista previa y un enlace de descarga de AMP374P6453BT1-C1H (archivo pdf) en la parte inferior de esta página. Total 12 Páginas
No Preview Available ! AVED MEMORY PRODUCTS Where Quality & Memory Merge AMP374P6453BT1-C1H/S 64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD DESCRIPTION AVED Memory Products AMP374P6453BT1-C1H/S is a 64M bit X 72 Synchronous Dynamic RAM high density memory module. The AVED Memory Products AMP374P6453BT1-C1H/S consists of eighteen CMOS 32M X 8 bit with 4 banks Synchronous DRAMs in TSOP-II 400mil package and a 2K EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The AVED Memory Products AMP374P6453BT1-C1H/S is a Dual In-Line Memory Module and is intended for mount- ing into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications. APPLICATION Main Memory unit for computer, Microcomputer memory, Refresh memory for CRT. FEATURES • Performance Ranges • Part Identification - AMP374P6453BT1-C1H/S 8k cycles/64ms Ref, TSOP, Gold Contact Plating - PC100 Compliant Part # Maximum Frequency/Speed AMP374P6453BT1-C1H/S PC100MHz (10ns @ CL=2) • Burst Mode Operation • Auto & Self Refresh capability (8k cycles/64ms) • LVTTL compatible inputs and outputs • Single 3.3V ± 0.3V power supply • MRS cycle with address key programs Latency (Access from column address) Burst Length (1, 2, 4, 8 & Full Page) Data Scramble (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock • Serial Presence Detect with EEPROM PIN NAMES Pin Nam e A0 - A12 BA0 - BA1 DQ0 - DQ63 CB0 - 7 CLK0 - CLK3 CKE0 - CKE1 CS0 - CS3 RAS CAS WE DQM0 - 7 VDD Vss VREF SDA SCL SA0 - 2 WP DU NC Function Address Input (multiplexed) Select Bank Data Input/Output Check Bit (Data-in/out) Clock Input Clock Enable Input Chip Select Input Row Address Strobe Column Address Strobe W rite Enable DQM Power Supply(3.3V) G ro u n d Power Supply for Reference Serial Address Data I/O Serial Clock Address in EEPROM W rite Protect Don’t Use No Connection Revision: 1.1 Revision Date: 11/2000 Document Number: 65830 Page Number: 1 of 12 http://www.Datasheet4U.com 1 page AVED MEMORY PRODUCTS Where Quality & Memory Merge AMP374P6453BT1-C1H/S 64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted) T A = 0 to 70ºC Symbol Test Condition ICC1 ICC2P ICC2PS ICC2N ICC2NS ICC3P ICC3PS ICC3N ICC3NS ICC4 ICC5 ICC6 Burst Length = 1 tRC ≥ tRC (min) IOL = 0mA CKE≤ VIL (max), tCC = 10ns CKE & CLK≤ VIL (max), tCC = ∞ CKE ≥ VIH (min), CS ≥ VIH (min), tCC = 10ns Input signals are changed one time during 20ns CKE ≥ VIH (min), CLK≤ VIL (max), tCC = ∞ Input signals are stable CKE≤ VIL (max), tCC = 10ns CKE & CLK≤ VIL(max), tCC = ∞ CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE ≥ VIH(min), CLK≤ VIL(max), tCC = ∞ Input signals are stable IOL = 0mA Page Burst 4 Banks activated tCCD = 2CLKS tRC ≥ tRC (min) CKE≤ 0.2V Version -1H 1,260 36 36 288 252 108 108 540 450 1,305 2,070 90 Unit mA mA mA mA mA mA mA mA ICC1: ICC2P: ICC2PS: ICC2N: ICC2NS: ICC3P: ICC3PS: ICC3N: ICC3NS: ICC4: ICC5 ICC6: Operating Current (one bank active) Precharge Standby Current in power-down mode Precharge Standby Current in power-down mode. Precharge Standby Current in non power-down mode. Precharge Standby Current in non power-down mode. Active Standby Current in power-down mode. Active Standby Current in power-down mode. Active Standby Current in non power-down mode (One Bank Active). Active Standby Current in non power-down mode (One Bank Active). Operating Current (Burst Mode) Refresh Current Self Refresh Current Notes: 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noted, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ). Revision: 1.1 Revision Date: 11/2000 Document Number: 65830 Page Number: 5 of 12 http://www.Datasheet4U.com 5 Page AVED MEMORY PRODUCTS Where Quality & Memory Merge AMP374P6453BT1-C1H/S 64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD SERIAL PRESENCE DETECT • Organization: 64M x 72 • Composition: 32M x 8*18 • # of rows in module: 2 • # of banks in component: 4 • Refresh: 8K/64ms Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36-61 Function Description # of bytes written into serial memory at module manufacturer Total # of bytes of SPD memory devices Fundamental memory type # of row address on this assembly # of column address on this assembly # of module rows on this assembly Data width of this assembly Data width of this assembly Voltage interface standard of this assembly SDRAM cycle time @ CAS latency 3 SDRAM access time from clock @ CAS latency 3 DIMM configuration type Refresh rate and type Primary SDRAM width Error checking SDRAM width Minimum clock delay for back-to-back random column address SDRAM device attributes: Burst lengths supported SDRAM device attributes: # of banks on SDRAM device SDRAM device attributes: CAS latency SDRAM device attributes: CS latency SDRAM device attributes: Write latency SDRAM module attributes SDRAM device attributes: General SDRAM cycle time @ CAS latency 2 SDRAM access time from clock @ CAS latency 2 SDRAM cycle time @ CAS latency 1 SDRAM access time from clock @ CAS latency 1 Minimum row precharge time (=tRP) Minimum row active to row active delay(tRRD) Minimum RAS to CAS delay (=tRCD) Minimum activate precharge time(=tRAS) Module row density Command and address signal input setup time Command and address signal input hold time Data signal input setup time Data signal input hold time Superset information (may be used in the future) Function Supported -1H 128 bytes 256 bytes (2K-bit) SDRAM 13 10 2 72 bits - LVTTL 10ns 6ns ECC 7.8 µs, support self refresh x8 x8 tCCD = 1CLK 1,2,4,8 & Full page 4 banks 2&3 0 CLK 0 CLK Non-buffered, Non- registered & redundant addressing ±10% voltage tolerance, Burst read, Single bit Write, precharge all, auto precharge 10ns 6ns - - 20ns 20ns 20ns 50ns 2 rows of 256MB 2ns 1ns 2ns 1ns - Hex Value -1H 80h Note 08h 04h 0Dh 1 0Ah 1 02h 48h 00h 01h A0h 2 60h 2 02h 82h 08h 08h 01h 8Fh 04h 06h 01h 01h 00h OEh A0h 2 60h 2 00h 00h 14h 14h 14h 32h 40h 20h 10h 20h 10h 00h Revision: 1.1 Revision Date: 11/2000 Document Number: 65830 Page Number: 11 of 12 http://www.Datasheet4U.com 11 Page

Páginas	Total 12 Páginas
PDF Descargar	[ Datasheet AMP374P6453BT1-C1H.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
AMP374P6453BT1-C1H	64M X 72 SDRAM DIMM	AVED
AMP374P6453BT1-C1S	64M X 72 SDRAM DIMM	AVED

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar