74HC4051A PDF даташит

Спецификация 74HC4051A изготовлена «Motorola Semiconductors» и имеет функцию, называемую «(74HC4051A / 74HC4053A) Analog Multiplexers / Demultiplexers».

Детали детали

Номер произв	74HC4051A
Описание	(74HC4051A / 74HC4053A) Analog Multiplexers / Demultiplexers
Производители	Motorola Semiconductors
логотип

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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Advance Information

Analog Multiplexers/

Demultiplexers

High–Performance Silicon–Gate CMOS

MC54/74HC4051A

MC74HC4052A

MC54/74HC4053A

The MC54/74HC4051A, MC74HC4052A and MC54/74HC4053A utilize

silicon–gate CMOS technology to achieve fast propagation delays, low ON

resistances, and low OFF leakage currents. These analog multiplexers/

J SUFFIX

demultiplexers control analog voltages that may vary across the complete

power supply range (from VCC to VEE).

The HC4051A, HC4052A and HC4053A are identical in pinout to the

CERAMIC PACKAGE

CASE 620–10

metal–gate MC14051AB, MC14052AB and MC14053AB. The Channel–Se-

lect inputs determine which one of the Analog Inputs/Outputs is to be

connected, by means of an analog switch, to the Common Output/Input.

When the Enable pin is HIGH, all analog switches are turned off.

The Channel–Select and Enable inputs are compatible with standard

CMOS outputs; with pullup resistors they are compatible with LSTTL

outputs.

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

D SUFFIX

SOIC PACKAGE

CASE 751B–05

These devices have been designed so that the ON resistance (Ron) is

more linear over input voltage than Ron of metal–gate CMOS analog

switches.

For a multiplexer/demultiplexer with channel–select latches, see

DW SUFFIX

SOIC WIDE PACKAGE

CASE 751G–02

HC4351A.

• Fast Switching and Propagation Speeds

• Low Crosstalk Between Switches

DT SUFFIX

TSSOP PACKAGE

CASE 948F–01

• Diode Protection on All Inputs/Outputs

• Analog Power Supply Range (VCC – VEE) = 2.0 to 12.0 V

• Digital (Control) Power Supply Range (VCC – GND) = 2.0 to 6.0 V

• Improved Linearity and Lower ON Resistance Than Metal–Gate

Counterparts

ORDERING INFORMATION

MC54HCXXXXAJ

MC74HCXXXXAN

MC74HCXXXXAD

MC74HCXXXXADW

Ceramic

Plastic

SOIC

SOIC Wide

• Low Noise

MC74HCXXXXADT TSSOP

• In Compliance With the Requirements of JEDEC Standard No. 7A

• Chip Complexity: HC4051A — 184 FETs or 46 Equivalent Gates

FUNCTION TABLE – MC54/74HC4051A

HC4052A — 168 FETs or 42 Equivalent Gates

HC4053A — 156 FETs or 39 Equivalent Gates

LOGIC DIAGRAM

Control Inputs

Enable

Select

CBA

ON Channels

MC54/74HC4051A

Single–Pole, 8–Position Plus Common Off

L LLL

L LLH

L LHL

X0 13

X1 14

ANALOG

INPUTS/

OUTPUTS

X2 15

X3 12

X4 1

MULTIPLEXER/

DEMULTIPLEXER

X5 5

X6 2

X7 4

CHANNEL

SELECT

INPUTS

A 11

B 10

ENABLE 6

PIN 16 = VCC

PIN 7 = VEE

PIN 8 = GND

COMMON

OUTPUT/

INPUT

Pinout: MC54/74HC4051A (Top View)

VCC X2 X1 X0 X3 A B C

16 15 14 13 12 11 10 9

12345678

X4 X6 X X7 X5 Enable VEE GND

L HH

HL L

HLH

HH L

HHH

XXX

NONE

X = Don’t Care

This document contains information on a new product. Specifications and information herein are subject to

change without notice.

10/97

REV 0

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MC54/74HC4051A MC74HC4052A MC54/74HC4053A

LOGIC DIAGRAM

MC74HC4052A

Double–Pole, 4–Position Plus Common Off

ANALOG

INPUTS/OUTPUTS

CHANNEL-SELECT

INPUTS

X0 12

X1 14

X2 15

X3 11

Y0 1

Y1 5

Y2 2

Y3 4

A 10

ENABLE 6

X SWITCH

Y SWITCH

13 X

COMMON

OUTPUTS/INPUTS

PIN 16 = VCC

PIN 7 = VEE

PIN 8 = GND

FUNCTION TABLE – MC74HC4052A

Control Inputs

Enable

Select

ON Channels

X = Don’t Care

Y0 X0

Y1 X1

Y2 X2

Y3 X3

NONE

Pinout: MC74HC4052A (Top View)

VCC X2 X1 X X0 X3 A

16 15 14 13 12 11 10

12345678

Y0 Y2 Y Y3 Y1 Enable VEE GND

LOGIC DIAGRAM

MC54/74HC4053A

Triple Single–Pole, Double–Position Plus Common Off

X0 12

X1 13

X SWITCH

14 X

Y0 2

ANALOG

INPUTS/OUTPUTS

Y1 1

Y SWITCH

15 Y

COMMON

OUTPUTS/INPUTS

Z0 5

Z1 3

A 11

CHANNEL-SELECT

INPUTS

B 10

ENABLE 6

Z SWITCH

PIN 16 = VCC

PIN 7 = VEE

PIN 8 = GND

NOTE: This device allows independent control of each switch.

Channel–Select Input A controls the X–Switch, Input B controls

the Y–Switch and Input C controls the Z–Switch

FUNCTION TABLE – MC54/74HC4053A

Control Inputs

Enable

Select

CBA

ON Channels

L L L L Z0 Y0 X0

L L L H Z0 Y0 X1

L L H L Z0 Y1 X0

L L H H Z0 Y1 X1

L H L L Z1 Y0 X0

L H L H Z1 Y0 X1

L H H L Z1 Y1 X0

L H H H Z1 Y1 X1

H XXX

NONE

X = Don’t Care

Pinout: MC54/74HC4053A (Top View)

VCC Y

16 15

X X1 X0 A B

14 13 12 11 10

12345678

Y1 Y0 Z1 Z Z0 Enable VEE GND

MOTOROLA

2 High–Speed CMOS Logic Data

DL129 — Rev 6

Free Datasheet http://www.Datasheet4U.com

No Preview Available !

MC54/74HC4051A MC74HC4052A MC54/74HC4053A

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎMAXIMUM RATINGS*

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol

Parameter

Value

Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVEE

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVIS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎI

Positive DC Supply Voltage

(Referenced to GND)

(Referenced to VEE)

– 0.5 to + 7.0

– 0.5 to + 14.0

Negative DC Supply Voltage (Referenced to GND)

– 7.0 to + 5.0

Analog Input Voltage

VEE – 0.5 to

VCC + 0.5

Digital Input Voltage (Referenced to GND)

DC Current, Into or Out of Any Pin

– 0.5 to VCC + 0.5

± 25

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPD Power Dissipation in Still Air, Plastic or Ceramic DIP†

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSOIC Package†

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTSSOP Package†

750

500

450

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTstg Storage Temperature Range

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTL Lead Temperature, 1 mm from Case for 10 Seconds

Plastic DIP, SOIC or TSSOP Package

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCeramic DIP

– 65 to + 150

260

300

* Maximum Ratings are those values beyond which damage to the device may occur.

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high–impedance cir-

cuit. For proper operation, Vin and

v vVout should be constrained to the

range GND (Vin or Vout) VCC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Unused outputs must be left open.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/_ C from 65_ to 125_ C

Ceramic DIP: – 10 mW/_ C from 100_ to 125_ C

SOIC Package: – 7 mW/_ C from 65_ to 125_ C

TSSOP Package: – 6.1 mW/_ C from 65_ to 125_ C

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVEE

Positive DC Supply Voltage

(Referenced to GND)

(Referenced to VEE)

Negative DC Supply Voltage, Output (Referenced to

GND)

2.0

– 6.0

6.0

12.0

GND

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVIS Analog Input Voltage

VEE VCC V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin Digital Input Voltage (Referenced to GND)

GND VCC V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVIO* Static or Dynamic Voltage Across Switch

1.2 V

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTA Operating Temperature Range, All Package Types

– 55 + 125 _ C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtr, tf Input Rise/Fall Time

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(Channel Select or Enable Inputs)

VCC = 2.0 V 0 1000 ns

VCC = 3.0 V 0

600

VCC = 4.5 V 0

500

VCC = 6.0 V 0

400

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ* For voltage drops across switch greater than 1.2V (switch on), excessive VCC current may be

drawn; i.e., the current out of the switch may contain both VCC and switch input components. The

reliability of the device will be unaffected unless the Maximum Ratings are exceeded.

High–Speed CMOS Logic Data

DL129 — Rev 6

MOTOROLA

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