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PDF RDA5807HS Data sheet ( Hoja de datos )
| Número de pieza | RDA5807HS | |
| Descripción | SINGLE-CHIP BROADCAST FM RADIO TUNER | |
| Fabricantes | RDA | |
| Logotipo |  |
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RDA5807HS
SINGLE-CHIP BROADCAST FM RADIO TUNER
Rev.1.2–July.2011
1 General Description
The RDA5807HS is a new generation single-chip
broadcast FM stereo radio tuner with fully
integrated synthesizer, IF selectivity and MPX
decoder. The tuner uses the CMOS process,
support multi-interface and require the least
external component. The package size is 3X3 mm
and is completely adjustment-free. All these make
it very suitable for portable devices.
The RDA5807HS has a powerful low-IF digital
audio processor, this make it have optimum sound
quality with varying reception conditions.
The RDA5807HS can be tuned to the worldwide
frequency band, even support frequency range
50~65MHz.
1.1 Features
CMOS single-chip fully-integrated FM tuner
Low power consumption
Total current consumption lower than 21mA at 3.0V
power supply when under normal situation
Support worldwide frequency band
50 -108 MHz
Support flexible channel spacing mode
100KHz, 200KHz, 50KHz and 25KHz
Digital low-IF tuner
Image-reject down-converter
High performance A/D converter
IF selectivity performed internally
Fully integrated digital frequency synthesizer
Fully integrated on-chip RF and IF VCO
Fully integrated on-chip loop filter
Autonomous search tuning
Support 32.768KHz crystal oscillator
Digital auto gain control (AGC)
20 19 18 17 16
LNAN 1
15 GPIO3
RFGND 2
LNAP 3
GND 4
GND
PAD
RDA 5807HS
14 GND
13 LOUT
12 ROUT
GND 5
11 GND
6 7 8 9 10
Figure 1-1. RDA5807HS Top View
Digital adaptive noise cancellation
Mono/stereo switch
Soft mute
High cut
Programmable de-emphasis (50/75 µs)
Receive signal strength indicator (RSSI) and SNR
Bass boost
Volume control and mute
I2S digital output interface
Line-level analog output voltage
32.768 KHz 12M,24M,13M,26M,19.2M,38.4MHz
Reference clock
2-wire serial control bus interface
Directly support 32Ω resistance loading
Integrated LDO regulator
1.8 to 5.5 V operation voltage
3X3mm 20 pin QFN package
Copyright © RDA Microelectronics Inc. 2006. All rights are reserved.
The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in
part without prior written permission of RDA.
Free Datasheet http://www.Datasheet4U.com
1 page  
RDA Microelectronics, Inc.
3.3 Delta-Sigma Synthesizer
The delta-sigma synthesizer generates the constant
clock signal to ADCs and DSP.
3.4 Power Supply
The RDA5807HS integrated one LDO which
supplies power to the chip. The external supply
voltage range is 1.8-5.5 V.
3.5 RESET and Control Interface select
The RDA5807HS is RESET itself When VIO is
Power up. And also support soft reset by trigger
02H BIT1 from 0 to 1. The control interface is
select by MODE Pin. The MODE Pin is low, I2C
Interface is select. The MODE Pin is set to VIO,
SPI Interface is select.
3.6 Control Interface
The RDA5807HS supports I2C control interface.
User could program the chip.
The I2C interface is compliant to I2C Bus
Specification 2.1. It includes two pins: SCLK and
SDIO. A I2C interface transfer begins with START
condition, a command byte and data bytes, each
byte has a followed ACK (or NACK) bit, and ends
with STOP condition. The command byte includes
a 7-bit chip address (0010000b) and a R/W bit.
The ACK (or NACK) is always sent out by receiver.
When in write transfer, data bytes is written out
from MCU, and when in read transfer, data bytes
is read out from RDA5807HS. There is no visible
register address in I2C interface transfers. The I2C
interface has a fixed start register address (0x02h
for write transfer and 0x0Ah for read transfer), and
an internal incremental address counter. If register
address meets the end of register file, 0x3Ah,
register address will wrap back to 0x00h. For write
transfer, MCU programs registers from register
0x02h high byte, then register 0x02h low byte,
then register 0x03h high byte, till the last register.
RDA5807HS always gives out ACK after every
RDA5807HS FM Tuner V1.2
byte, and MCU gives out STOP condition when
register programming is finished. For read transfer,
after command byte from MCU, RDA5807HS
sends out register 0x0Ah high byte, then register
0x0Ah low byte, then register 0x0Bh high byte, till
receives NACK from MCU. MCU gives out ACK
for data bytes besides last data byte. MCU gives
out NACK for last data byte, and then
RDA5807HS will return the bus to MCU, and
MCU will give out STOP condition.
Details refer to RDA5807HS Programming Guide.
3.7 I2S Audio Data Interface
The RDA5807HS supports I2S (Inter_IC Sound
Bus) audio interface. The interface is fully
compliant with I2S bus specification. When setting
I2SEN bit high, RDA5807HS will output SCK, WS,
SD signals from GPIO3, GPIO1, GPIO2 as I2S
master and transmitter, the sample rate is
48Kbps，44.1kbps,32kbps….. RDA5807HS also
support as I2S slaver mode and transmitter, the
sample rate is less than 100kbps.
Details refer to RDA5807HS Programming Guide.
3.8 GPIO Outputs
The RDA5807HS has three GPIOs. The function
of GPIOs could programmed with bits GPIO1[1:0],
GPIO2[1:0], GPIO3[1:0] and I2SEN.
If I2SEN is set to low, GPIO pins could be
programmed to output low or high or high-Z, or be
programmed to output interrupt and stereo
indicator with bits GPIO1[1:0], GPIO2[1:0],
GPIO3[1:0]. GPIO2 could be programmed to
output a low interrupt (interrupt will be generated
only with interrupt enable bit STCIEN is set to high)
when seek/tune process completes. GPIO3 could
be programmed to output stereo indicator bit ST.
Constant low, high or high-Z functionality is
available regardless of the state of VDD supplies
or the ENABLE bit.
The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in
part without prior written permission of RDA.
Page 4 of 22
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5 Page 
RDA Microelectronics, Inc.
REG BITS
NAME
5:4 GPIO3[1:0]
3:2 GPIO2[1:0]
1:0 GPIO1[1:0]
05H 15
INT _MODE
14:8
SEEKTH[6:0]2
7:6 LNA_PORT_SEL[1:0]
5:4 LNA_ICSEL_BIT[1:0]
3:0 VOLUME[3:0]
06H 14
Open_mode
12 I2s_mode_select
7:4 I2s_ws_cnt[4:0]
Only valid
in master mode
RDA5807HS FM Tuner V1.2
FUNCTION
DEFAULT
General Purpose I/O 3.
00 = High impedance
01 = Mono/Stereo indicator (ST)
10 = Low
11 = High
General Purpose I/O 2.
00 = High impedance
01 = Interrupt (INT)
10 = Low
11 = High
General Purpose I/O 1.
00 = High impedance
01 = Reserved
10 = Low
11 = High
If 0, generate 5ms interrupt;
00
00
00
1
If 1, interrupt last until read reg0CH action
occurs.
Seek SNR threshold value when 0001000
seek_mode[2:0]=001
LNA input port selection bit:
10
00: no input
01: LNAN
10: LNAP
11: dual port input
Lna working current bit:
00
00=1.8mA
01=2.5mA
10=3.1 mA
11=3.8mA
DAC Gain Control Bits (Volume).
0000=min; 1111=max
Volume scale is logarithmic
When 0000, output mute and output
impedance is very large
Open test register mode.
0=only open behind registers reading function
1=open behind registers writing function
If 0, master mode;
1111
0
0
If 1, slave mode.
4'b1000: WS_STEP_48;
4'b0111: WS_STEP=44.1kbps;
4'b0110: WS_STEP=32kbps;
4'b0101: WS_STEP=24kbps;
4'b0100: WS_STEP=22.05kbps;
4'b0011: WS_STEP=16kbps;
4'b0010: WS_STEP=12kbps;
4'b0001: WS_STEP=11.025kbps;
4'b0000: WS_STEP=8kbps;
0000
2 This value is used when 0x20H_bit<14:12> ( Seek_mode )=001, default seek mode is Audio_SNR seek mode.
The information contained herein is the exclusive property of RDA and shall not be distributed, reproduced, or disclosed in whole or in
part without prior written permission of RDA.
Page 10 of 22
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