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PDF LS037V7DD05 Data sheet ( Hoja de datos )

Número de pieza LS037V7DD05
Descripción CG-Silicon TFT-LCD module
Fabricantes Sharp 
Logotipo Sharp Logotipo



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No Preview Available ! LS037V7DD05 Hoja de datos, Descripción, Manual

No. LCP-04006A
DATE Mar.3.2004
TECHNICAL LITERATURE
FOR
CG-Silicon TFT-LCD module
MODEL No. LS037V7DD05
TENTATIVE
The technical literature is subject to change without notice.
So , please contact Sharp or its representative before designing
your product based on this literature.
SHARP CORPORATION
MOBILE LIQUID CRYSTAL DISPLAY GROUP
Free Datasheet http://www.nDatasheet.com

1 page




LS037V7DD05 pdf
(5)Input/Output terminal
5-1) TFT-LCD panel and Backlight driving section
Table2
Pin No. Symbol I/O
Description
1
VL1
Power supply for LED ( High Voltage )
2 NC
3
VL2
Power supply for LED ( Low Voltage )
4 VSSD Power supply of driver ( Low level_1)
5 VSHD Power supply of digital
6 DGND Ground (digital )
7
CLS
I Clock signal of gate driver
8 DGND Ground (digital )
9
SPS
I Start signal of gate driver
10 U/L I Selection for vertical scanning direction
11
MOD
I Control signal of driver
12 VDD Power supply of driver (High level)
13 VCOM I Common electrode driving signal
14 DGND Ground (digital )
15 SPR I/O Sampling start signal
16 DGND Ground (digital )
17 VSHA Power supply ( analog )
18
LBR
I Selection for horizontal scanning direction
19 NC
20
REV
I Reverse control signal
21 DGND Ground (digital )
22 B5 I BLUE data signal (MSB)
23 B4 I BLUE data signal
24 B3 I BLUE data signal
25 B2 I BLUE data signal
26 B1 I BLUE data signal
27 B0 I BLUE data signal (LSB)
28 DGND Ground (digital )
29 LP I Data latch signal of source driver
30 SPL I/O Sampling start signal
31 DGND Ground (digital )
32 DCLK I Data sampling clock signal
33 DGND Ground (digital )
34 G5 I GREEN data signal (MSB)
35 G4 I GREEN data signal
36 G3 I GREEN data signal
LCP-04006A-3
Remarks
Note5-1
Note5-2
Note5-3
Note5-3
Note5-3
Free Datasheet http://www.nDatasheet.com

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LS037V7DD05 arduino
LCP-04006A-9
Teminal
Parameter
Clock frequency
Rising time of clock
Falling time of clock
Setup time of clock
Pulse width of clock (Low1)
CLS
Pulse width of clock (Low2)
Pulse width of clock(High)
SPS
Phase SPSCLS
Phase SPSCLS
Phase SPSCLS
Phase SPSCLS
Rising time of start pulse
Falling time of start pulse
Frequency of start pulse
VCOM
CsCOM
Setup time of VCOM and CsCOM
Hold time of VOM and CsCOM
Symbol
fcls
Trcls
Tfcls
Tsucls
Twclsl1
Twclsl2
Twclsh
Tsps-cls1
Tsps-cls2
Tsps-cls3
Tsps-cls4
Trsps
Tfsps
fsps
Tsucom
Thcom
VGA
QVGA
VGA
QVGA
VGA
QVGA
VGA
QVGA
VGA
QVGA
VGA
QVGA
VGA
QVGA
Min.
35.5
17.9
100
2
3
2
3
23
46.1
1
1
1
1
55
55
2
4
1
2
Typ.
60
60
Max.
39.5
19.9
50
50
4.5
9
4.5
9
50
50
61.3
61.6
Unit
kHz
ns
ns
ns
μs
μs
μs
μs
μs
μs
μs
ns
ns
Hz
μs
μs
【Note 7-6】There must be only one up-edge of DCLK(includes Tsusp and Thsp time) in the
period SPL(orSPR)=“High”
Free Datasheet http://www.nDatasheet.com

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