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95V857 PDF даташит

Спецификация 95V857 изготовлена ​​​​«Integrated Circuit Systems» и имеет функцию, называемую « ICS95V857».

Детали детали

Номер произв 95V857
Описание ICS95V857
Производители Integrated Circuit Systems
логотип Integrated Circuit Systems логотип 

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95V857 Даташит, Описание, Даташиты
Integrated
Circuit
Systems, Inc.
ICS95V8 5 7
2.5V Wide Range Frequency Clock Driver (45MHz - 233MHz)
Recommended Application:
• DDR Memory Modules / Zero Delay Board Fan Out
• Provides complete DDR registered DIMM solution
with ICSSSTVF16857, ICSSSTVF16859 or
ICSSSTV32852
Product Description/Features:
• Low skew, low jitter PLL clock driver
• 1 to 10 differential clock distribution (SSTL_2)
• Feedback pins for input to output synchronization
• PD# for power management
• Spread Spectrum-tolerant inputs
• Auto PD when input signal removed
Specifications:
• Meets PC3200 Class A+ specification for DDR-I 400
support
• Covers all DDRI speed grades
Switching Characteristics:
• CYCLE - CYCLE jitter: <50ps
• OUTPUT - OUTPUT skew: <40ps
• Period jitter: ±30ps
Pin Configuration
GND
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
GND
CLKC2
CLKT2
VDD
VDD
CLK_INT
CLK_INC
VDD
AVDD
AGND
GND
CLKC3
CLKT3
VDD
CLKT4
CLKC4
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 GND
47 CLKC5
46 CLKT5
45 VDD
44 CLKT6
43 CLKC6
42 GND
41 GND
40 CLKC7
39 CLKT7
38 VDD
37 PD#
36 FB_INT
35 FB_INC
34 VDD
33 FB_OUTC
32 FB_OUTT
31 GND
30 CLKC8
29 CLKT8
28 VDD
27 CLKT9
26 CLKC9
25 GND
48-Pin TSSOP/TVSOP
6.10 mm Body, 0.50 mm Pitch = TSSOP
4.40 mm Body, 0.40 mm Pitch = TVSOP
Block Diagram
Functionality
INPUTS
OUTPUTS
PLL State
AVDD PD# CLK_INT CLK_INC CLKT CLKC FB_OUTT FB_OUTC
GND H
L
H LH L
H Bypassed/off
GND
2.5V
(nom)
2.5V
(nom)
2.5V
(nom)
2.5V
(nom)
2.5V
(nom)
H
L
L
H
H
X
HL
LH
HL
LH
HL
<20MHz)(1)
HL
ZZ
ZZ
LH
HL
ZZ
H
Z
Z
L
H
Z
L Bypassed/off
Z off
Z off
H on
L on
Z off
PD#
FB_INT
FB_INC
CLK_INC
CLK_INT
Control
Logic
PLL
0674U01/27/09
FB_OUTT
FB_OUTC
CLKT0
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
CLKT5
CLKC5
CLKT6
CLKC6
CLKT7
CLKC7
CLKT8
CLKC8
CLKT9
CLKC9
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95V857 Даташит, Описание, Даташиты
ICS95V8 5 7
0674U01/27/09
Pin Configuration
123456
A
B
C
D
E
F
G
H
J
K
56-Ball BGA
Top View
12
A CLKT0 CLKC0
B CLKC1 CLKT1
C GND
GND
D CLKT2 CLKC2
E VDD
VDD
F CLK_INT CLK_INC
G VDD
AVDD
H AGND GND
J CLKC3 CLKT3
K CLKT4 CLKC4
3
GND
VDD
NC
NC
NB
NB
NC
NC
VDD
GND
4
GND
VDD
NC
NC
NB
NB
NC
NC
VDD
GND
56
CLKC5 CLKT5
CLKT6 CLKC6
GND
GND
CLKC7 CLKT7
VDD
PD#
FB_INC FB_INT
FB_OUTC VDD
GND FB_OUTT
CLKT8 CLKC8
CLKC9 CLKT9
40 31
GND 1
CLKC2
CLKT2
VDD
CLK_INT
CLK_INC
VDD
AVDD
AGND
GND 10
ICS95V857
30 CLKC7
CLKT7
VDD
PD#
FB_INT
FB_INC
VDD
VDD
FB_OUTC
21 FB_OUTT
11 20
40-Pin MLF
2
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95V857 Даташит, Описание, Даташиты
ICS95V8 5 7
Pin Descriptions
PIN NAME
TYPE
DESCRIPTION
VDD
PWR Power supply, 2.5V
GND
AVDD
AGND
CLKT(9:0)
CLKC(9:0)
CLK_INC
CLK_INT
FB_OUTC
FB_OUTT
FB_INT
FB_INC
PD#
PWR Ground
PWR
PWR
OUT
Analog power supply, 2.5V
Analog ground
"True" Clock of differential pair outputs
OUT "Complementary" clocks of differential pair outputs
IN "Complementary" reference clock input
IN
OUT
OUT
IN
IN
IN
"True" reference clock input
"Complementary" Feedback output, dedicated for external feedback. It
switches at the same frequency as the CLK. This output must be wired
to FB_INC
"True" " Feedback output, dedicated for external feedback. It switches
at the same frequency as the CLK. This output must be wired to
FB_INT
"True" Feedback input, provides feedback signal to the internal PLL for
synchronization with CLK_INT to eliminate phase error
"Complementary" Feedback input, provides signal to the internal PLL
for synchronization with CLK_INC to eliminate phase error
Power Down. LVCMOS input
This PLL Clock Buffer is designed for a VDD of 2.5V, an AVDD of 2.5V and differential data input and output levels.
The ICS95V857 is a zero delay buffer that distributes a differential clock input pair (CLK_INC, CLK_INT) to ten
differential pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock output (FB_OUT,
FB_OUTC).The clock outputs are controlled by the input clocks (CLK_INC, CLK_INT), the feedback clocks (FB_INT,
FB_INC), the 2.5-V LVCMOS input (PD#) and the Analog Power input (AVDD).When input (PD#) is low while power is
applied, the receivers are disabled, the PLL is turned off and the differential clock outputs are tri-stated. When AVDD
is grounded, the PLL is turned off and bypassed for test purposes.
When the input frequency is less than the operating frequency of the PLL, appproximately 20MHz, the device will enter
a low power mode. An input frequency detection circuit on the differential inputs, independent from the input buffers,
will detect the low frequency condition and perform the same low power features as when the (PD#) input is low.When
the input frequency increases to greater than approximately 20 MHz, the PLL will be turned back on, the inputs and
outputs will be enabled and PLL will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input
clock pair (CLK_INC, CLK_INT).
The PLL to the ICS95V857 clock driver uses the input clocks (CLK_INC, CLK_INT) and the feedback clocks (FB_INT,
FB_INC) provide high-performance, low-skew, low-jitter, output differential clocks (CLKT[0:9], CLKC[0:9]). The
ICS95V857 is also able to track Spread Spectrum Clock (SSC) for reduced EMI.
The ICS95V857 is characterized for operation from 0°C to 85°C, and will meet JEDEC Standard 82-1 and 82-1A Class
A+ for registered DDR clock drivers.
0674U01/27/09
3
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Номер в каталогеОписаниеПроизводители
95V857 ICS95V857Integrated Circuit Systems
Integrated Circuit Systems

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