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Rev. 0.2, May. 2010
K9F2G08U0C
Advance
2Gb C-die NAND Flash
Single-Level-Cell (1bit/cell)
datasheet
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K9F2G08U0C
datasheet
Advance Rev. 0.2
FLASH MEMORY
2.4 Valid Block
Parameter
K9F2G08U0C
Symbol
NVB
Min
2,008
Typ.
-
Max
2,048
Unit
Blocks
NOTE :
1) The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both
cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program factory-marked bad blocks. Refer to the
attached technical notes for appropriate management of invalid blocks.
2) The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/528Byte ECC.
3) The number of valid block is on the basis of single plane operations, and this may be decreased with two plane operations.
2.5 AC Test Condition
(K9F2G08U0C-XCB0 :TA=0 to 70°C, K9F2G08U0C-XIB0:TA=-40 to 85°C, K9F2G08U0C: Vcc=2.7V~3.6V unless otherwise noted)
Parameter
K9F2G08U0C
Input Pulse Levels
0V to Vcc
Input Rise and Fall Times
5ns
Input and Output Timing Levels
Vcc/2
Output Load
1 TTL GATE and CL=50pF
2.6 Capacitance(TA=25°C, VCC= 3.3V, f=1.0MHz)
Item
Input/Output Capacitance
Input Capacitance
Symbol
CI/O
CIN
Test Condition
VIL=0V
VIN=0V
Min
-
-
Max
10
10
Unit
pF
pF
NOTE :
Capacitance is periodically sampled and not 100% tested.
2.7 Mode Selection
CLE
H
L
H
L
L
L
X
X
X
X
X
ALE
L
H
L
H
L
L
X
X
X
X(1)
X
CE
L
L
L
L
L
L
X
X
X
X
H
WE
H
X
X
X
X
X
NOTE :
1) X can be VIL or VIH.
2) WP should be biased to CMOS high or CMOS low for standby.
RE WP
Mode
HX
Command Input
Read Mode
HX
Address Input(5clock)
HH
Command Input
Write Mode
HH
Address Input(5clock)
H H Data Input
X Data Output
H X During Read(Busy)
X H During Program(Busy)
X H During Erase(Busy)
X L Write Protect
X 0V/VCC(2) Stand-by
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